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1. 发明授权

US09135834B2 Apparatus and method to prevent side channel power attacks in advanced encryption standard using floating point operation 有权
标题翻译：使用浮点运算在高级加密标准中防止侧信道功率攻击的装置和方法
公开(公告)号：US09135834B2
公开(公告)日：2015-09-15
申请号：US14161780
申请日：2014-01-23
申请人： THE GOVERNMENT OF THE UNITED STATES AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE
发明人： Lisa Weyna , John W. Rooks
IPC分类号： H04L9/30 , G09C1/00 , H04L9/00 , H04L9/06
CPC分类号： G09C1/00 , H04L9/003 , H04L9/0631 , H04L2209/12
摘要： Apparatus and method for obscuring round 1 power consumption of hardware implementation of the AES algorithm. By simultaneously executing a processor floating point operation while executing round 1 of the AES algorithm power consumption of the AddRoundKey transformation is obscured. This prevents the opportunity to determine the AES key value during a side channel power attack.
摘要翻译：用于模糊AES算法的硬件实现的第1轮功耗的装置和方法。通过在执行AES算法的第1轮的同时执行处理器浮点运算，AddRoundKey变换的功耗被遮蔽。这样就无法在侧信道电源攻击中确定AES密钥值。

2. 发明授权

US09024661B2 Glitch free clock multiplexer 有权
标题翻译：无毛刺时钟多路复用器
公开(公告)号：US09024661B2
公开(公告)日：2015-05-05
申请号：US14150843
申请日：2014-01-09
申请人： The United States of America as Represented by the Secretary of the Air Force
发明人： John W. Rooks
IPC分类号： H03K19/00 , H03K17/00 , H03K21/00
CPC分类号： H03K19/0016
摘要： Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different (unrelated) clocks without causing erratic behavior.
摘要翻译：用于在集成电路上的两个时钟源之间无毛刺切换的装置。时钟提供来自单个源的时钟，可以打开和关闭时钟，而不会产生部分脉冲。到各个时钟加速器的控制电路提供了关闭所有时钟关闭等待最长时钟周期的时间的能力。通过将时钟与或门并入，在从一个时钟切换到另一个时钟之前关闭所有时钟，可以从各个时钟输入创建无毛刺的时钟脉冲序列。由于时钟故障可能导致集成电路中的不稳定行为，本发明允许在不同的（不相关）时钟之间切换，而不会引起不稳定的行为。

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