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1. 发明授权

US5223002A Method of making polyaniline solid electrolyte capacitor 失效
标题翻译：制备聚苯胺固体电解电容器的方法
公开(公告)号：US5223002A
公开(公告)日：1993-06-29
申请号：US786315
申请日：1991-10-31
申请人： Sidney D. Ross
发明人： Sidney D. Ross
IPC分类号： H01G9/02 , H01G9/025
CPC分类号： H01G9/025 , Y10T29/417 , Y10T29/435
摘要： Highly conducting polyaniline is produced in situ in a tantalum capacitor by subjecting an excess of monomeric aniline to a solution having a low concentration of ammonium persulfate reagent. The monomer is oxidized by the reagent in preference to the polymer, so that the presence of excess monomer protects the polymer as it is produced against further oxidation to a less conductive species.
摘要翻译：通过将过量的单体苯胺过滤到具有低浓度的过硫酸铵试剂的溶液中，在钽电容器中原位生产高导电性聚苯胺。单体优先于聚合物被试剂氧化，使得过量单体的存在保护了聚合物，因为它被产生以防止进一步氧化成较不导电的物质。

2. 发明授权

US5057973A Solid electrolyte capacitor with integral stamped fuze 失效
标题翻译：固体电解电容器，带有一体式加盖引信
公开(公告)号：US5057973A
公开(公告)日：1991-10-15
申请号：US589240
申请日：1990-09-28
申请人： Didier Gouvernelle , Michel Andrepierre
发明人： Didier Gouvernelle , Michel Andrepierre
IPC分类号： H01G9/00
CPC分类号： H01G9/0003 , Y10T29/417
摘要： A solid electrolyte capacitor in a block of electrically insulative resin is provided with two electrodes connected by respective connecting tangs to output leads (+, -) and to a fuze test lead; one connecting tang (6) is formed by a first section (6B) fixed to one of the electrodes and projecting out of the resin block to form the fuze test lead, and a second section (6A) projecting out of the resin block to form a conventional terminal; an elongate strip (10) forms the fuze in one piece with the sections (6A,6B) so as to provide the only electrical connection between the sections; the fuze is coated with a supporting mass of thermally insulative resin extending between the two sections and embedded in the resin block.
摘要翻译：在电绝缘树脂块中的固体电解质电容器设置有两个电极，通过相应的连接脚连接到输出引线（+30， - ）和引信测试引线; 一个连接脚（6）由固定到一个电极上的第一部分（6B）形成，并从树脂块突出出来形成引信测试引线;以及第二部分（6A），突出到树脂块之外以形成常规终端; 细长条（10）与部分（6A，6B）一体形成引信，以便在部分之间提供唯一的电连接; 引信物被涂覆有在两部分之间延伸并嵌入树脂块中的支撑质量的绝热树脂。

3. 发明授权

US5011067A Method for attaching a fuse wire to a lead frame 失效
标题翻译：将保险丝连接到引线框架的方法
公开(公告)号：US5011067A
公开(公告)日：1991-04-30
申请号：US500351
申请日：1990-03-26
申请人： Robert L. Foisy
发明人： Robert L. Foisy
IPC分类号： B23K23/00 , H01H85/143
CPC分类号： B23K23/00 , H01H85/143
摘要： A standard tinned nickel-iron alloy lead frame has a plurality of pairs of extending tab portion positioned in a straight row. A long straight piece of an exothermically alloyable fuse wire, with a core of aluminum coaxially clad with palladium in approximately equal volumes, is held in contact with the plurality of pairs of lead frame tabs. Heat is applied to the fuse strand at two points; namely, on one and the other sides of each pair of tabs initiating progressive alloying in two directions from each heated point. When the progressive alloying and melting of the fuse strand reaches a tab, the tab is heated and heat sinks the fuse strand to stop the progressive alloying and melting. There is simultaneously formed a metallurgical bond between the ends of each remaining elemental fuse strand, respectively, and each of the pair of tabs that are bridged by that remaining elemental strand.
摘要翻译：标准镀锡镍铁合金引线框架具有定位在直列中的多对延伸突片部分。具有与大致相等体积的钯同轴包覆的铝的芯的耐热合金熔丝的长直的片与多对引线框突片保持接触。在两点对热熔丝进行加热; 即，在每个加热点的两个方向上，每对翼片的一侧和另一侧开始逐渐合金化。当熔丝的渐进合金化和熔化达到拉片时，拉片被加热，并且将熔丝线散开，以阻止渐进的合金化和熔化。分别在每个剩余元素熔丝线的端部之间同时形成冶金结合，并且由该剩余元素线桥接的一对突片中的每一个。

4. 发明授权

US5001073A Method for making bipolar/CMOS IC with isolated vertical PNP 失效
标题翻译：具有隔离垂直PNP的双极/ CMOS IC的方法
公开(公告)号：US5001073A
公开(公告)日：1991-03-19
申请号：US553029
申请日：1990-07-16
申请人： Wing K. Huie
发明人： Wing K. Huie
IPC分类号： H01L21/761 , H01L21/8249
CPC分类号： H01L21/8249 , H01L21/761 , Y10S148/009
摘要： The manufacture of an integrated circuit including an isolated vertical PNP, an isolated vertical NPN and isolated CMOS transistors is described. The PNP transistor has a shallow densely doped emitter made simultaneously with the source and drain of the PMOS transistor. The PNP base is made simultaneously with lightly doped portions of the LDD source and drain of the NMOS transistor. The PNP collector is made simultaneously with the P-well in which the NMOS transistor is formed. A P-buried layer in the isolated vertical PNP transistor provides a low collector resistance and is formed simultaneously with the P-buried layer of the NMOS transistor that extends the P-well there and better isolates the NMOS transistor from the substrate. And the N-buried layer providing superior isolation of the PNP with respect to the substrate is formed simultaneously with the N-buried layer of the vertical NPN transistor. All four of these transistors provide and are well suited for use in analog signal handling circuits. All are capable of operating at up to 15 volts. And both bipolar transistors have a high gain bandwidth.
摘要翻译：描述了包括隔离垂直PNP，隔离垂直NPN和隔离CMOS晶体管的集成电路的制造。 PNP晶体管具有与PMOS晶体管的源极和漏极同时形成的浅密度掺杂发射极。 PNP基极与NMOS晶体管的LDD源极和漏极的轻掺杂部分同时进行。 PNP集电极与形成NMOS晶体管的P阱同时进行。隔离垂直PNP晶体管中的P型掩埋层提供低集电极电阻，并且与NMOS晶体管的P埋层同时形成，从而在其上延伸P阱，并且更好地将NMOS晶体管与衬底隔离。并且与垂直NPN晶体管的N埋层同时形成提供PNP相对于衬底的优异隔离的N埋层。这些晶体管中的所有四个都提供并且非常适用于模拟信号处理电路。所有这些都能够工作在最高15伏。并且两个双极晶体管都具有高增益带宽。

5. 发明授权

US4989119A Solid electrolyte capacitor with testable fuze 失效
标题翻译：固体电解电容器，带可测试引信
公开(公告)号：US4989119A
公开(公告)日：1991-01-29
申请号：US474572
申请日：1990-02-02
申请人： Didier Gouvernelle
发明人： Didier Gouvernelle
IPC分类号： H01G9/00
CPC分类号： H01G9/0003 , Y10T29/417
摘要： A solid electrolytic capacitor embedded in an electrically insulating resin block has a capacitor body fitted with two electrodes which are connected by two connecting lugs, those of the output terminals (+, -) and a fuze test. One of the connecting lugs is formed of a first section attached to one of electrodes of the capacitor body and leading outside the resin block to form the fuze test terminal, and of a second section electrically insulated with respect to first section and the capacitor body and leading outside the resin block to form a normal operating terminal. The fuze element alone establishes an electric link between the first and second sections while being surrounded by the supporting mass of thermally insulating resin reaching from one of the sections to the other, while itself being embedded in the resin.
摘要翻译：嵌入电绝缘树脂块中的固体电解电容器具有装配有两个电极的电容器体，两个电极通过两个连接凸耳（输出端子（+， - ））和引信测试连接。连接凸耳中的一个由连接到电容器主体的电极之一并引导到树脂块外部的第一部分形成引信测试端子，以及相对于第一部分和电容器主体电绝缘的第二部分，以及引导树脂块外面形成正常的操作终端。引信元件单独建立在第一和第二部分之间的电连接，同时被从其中一个部分到另一部分的绝热树脂的支撑质量包围，同时本身嵌入树脂中。

6. 发明授权

US4935698A Sensor having dual Hall IC, pole piece and magnet 失效
标题翻译：传感器具有双霍尔IC，极片和磁铁
公开(公告)号：US4935698A
公开(公告)日：1990-06-19
申请号：US318265
申请日：1989-03-03
申请人： Hideki Kawaji , Peter J. Gilbert
发明人： Hideki Kawaji , Peter J. Gilbert
IPC分类号： G01B7/14 , H03K17/95
CPC分类号： H03K17/9517 , G01B7/14
摘要： A Hall elements and magnet assembly for use as a proximity detector includes a magnet, a pole piece mounted to one pole end of the magnet and an integrated circuit having two side-by-side Hall elements, an amplifier, interconnecting wiring providing the difference voltage between the two Hall output voltages at the input of the amplifier, and a Schmitt trigger circuit. The integrated circuit is mounted to the pole piece at the pole end of the magnet. The pole piece is a ferromagnetic member which is thinner in the center than at the periphery for achieving a highly uniform field strength across the surface of the magnet pole end toward reducing the criticality of the position of mounting of the integrated circuit in manufacturing and for extending the range of gap dimensions between a passing ferromagnetic article and the assembly for which proper detection of the passing article can be made to occur. The term "ferromagnetic" as used herein means any material with a relative permeability greater than unity and preferably greater than 100.
摘要翻译：用作接近检测器的霍尔元件和磁体组件包括磁体，安装到磁体的一个极端的极片和具有两个并排霍尔元件的集成电路，放大器，提供差分电压的互连布线放大器输入端的两个霍尔输出电压和施密特触发电路之间。集成电路安装在磁铁极端的极片上。极片是一个铁磁构件，其中心比外围薄，以便在磁极端部的表面上实现高度均匀的场强，从而降低集成电路在制造中的安装位置的关键性并延长通过的铁磁制品与通过制品的适当检测的组件之间的间隙尺寸可以进行。本文所用的术语“铁磁”是指相对磁导率大于1，优选大于100的任何材料。

7. 发明授权

US4925808A Method for making IC die with dielectric isolation 失效
标题翻译：用绝缘隔离制造IC芯片的方法
公开(公告)号：US4925808A
公开(公告)日：1990-05-15
申请号：US328211
申请日：1989-03-24
申请人： William E. Richardson
发明人： William E. Richardson
IPC分类号： H01L21/762 , H01L21/78 , H01L21/82
CPC分类号： H01L21/76297 , H01L21/78 , H01L21/82
摘要： The method includes forming in one surface of an N+ silicon wafer a matrix of uniformly deep V-shaped grooves, growing one SiO.sub.2 over the one surface and the walls of the grooves, forming over the opposite wafer surface a thick self-supporting polycrystalline layer, progressively removing portions of the original silicon wafer until the bottoms of the grooves are detected to leave separate patches of the original N+ silicon wafer material and then growing a thin (e.g. 6 microns) P-doped layer of epitaxial silicon on the exposed N+ silicon layer patch portions now isolated and defined by the grooves. A figure-eight pattern of trenches is formed in each silicon island completely through the P epitaxial layer and each of the underlying N+ buried patches but stopped at the SiO.sub.2 layer. An N+ plug is formed through the epitaxial layer to each N+ patch. Metal conductors complete the formation of a JFET transistor in each island bounded and defined by one of the closed loops or annular portions of the figure-eight-patterned trenches. The wafer is then sawed apart along all the V-shaped grooves providing a plurality of IC die, each having two dielectrically isolated JFET transistors.
摘要翻译：该方法包括在N +硅晶片的一个表面上形成均匀深的V形槽的基体，在一个表面上生长一个SiO 2，在该相对的晶片表面上形成厚的自支撑多晶层，逐渐去除原始硅晶片的部分，直到检测到凹槽的底部以留下原始N +硅晶片材料的分开的贴片，然后在暴露的N +硅层上生长薄（例如6微米）的外延硅的P掺杂层现在由凹槽隔离并限定的贴片部分。在每个硅岛中完全通过P外延层和每个下面的N +掩埋贴片形成图形八个图案的沟槽，但是停止在SiO 2层。通过外延层向每个N +贴片形成N +插头。金属导体在由八个图案化的沟槽中的一个闭环或环形部分限定和限定的每个岛中完成JFET晶体管的形成。然后将晶片沿所有V形槽锯分开，提供多个IC管芯，每个具有两个介电隔离的JFET晶体管。

8. 发明授权

US4914051A Method for making a vertical power DMOS transistor with small signal bipolar transistors 失效
标题翻译：制造具有小信号双极晶体管的垂直功率DMOS晶体管的方法
公开(公告)号：US4914051A
公开(公告)日：1990-04-03
申请号：US281593
申请日：1988-12-09
申请人： Wing K. Huie , Alexander H. Owens , David S. Pan , Michael J. Zunino
发明人： Wing K. Huie , Alexander H. Owens , David S. Pan , Michael J. Zunino
IPC分类号： H01L21/28 , H01L21/761 , H01L21/8249 , H01L27/06
CPC分类号： H01L29/66712 , H01L21/28 , H01L21/761 , H01L21/8249 , H01L27/0623 , H01L29/7302 , H01L29/7322 , H01L29/7809 , H01L29/0696 , Y10S148/126
摘要： A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.
摘要翻译：硅集成电路通过包括在DMOS晶体管和NPN晶体管中的基极区域中同时形成多个D阱区域的方法，在单独的外延阱中包括垂直功率DMOS晶体管和垂直NPN晶体管，并且包括同时形成元素源极区域和发射极区域。分别在DMOS和NPN晶体管中同时提供N型掩埋层。同时形成两个分别将两个掩埋层连接到集成电路管芯的外延表面的N +插头。这些经济上有吸引力的同步步骤都不需要任何装置的偏差与最佳几何形状。还公开了用于形成小信号CMOS晶体管的兼容和集成步骤。该方法还包括DMOS晶体管以及CMOS晶体管中的栅极，源极和沟道区域的完全自对准。

9. 发明授权

US4899258A Solid electrolyte capacitor with integral fuse 失效
标题翻译：带集成保险丝的固体电解电容器
公开(公告)号：US4899258A
公开(公告)日：1990-02-06
申请号：US324131
申请日：1989-03-16
申请人： Didier Gouvernelle
发明人： Didier Gouvernelle
IPC分类号： H01G9/12 , H01G9/00
CPC分类号： H01G9/0003 , Y10T29/417
摘要： A solid electrolyte capacitor body is embedded in an electrically insulative block of resin. Output terminals each connected to a respective electrode of the capacitor body project from the block. One output terminal includes a first section fixed to one of the electrodes and a second section electrically insulated from the first section and the capacitor body. A fusible member alone establishes electrical connection between the first and second sections. The fusible member is embedded in a rigid thermally insulative resin which extends between the first and second sections to couple them together mechanically.
摘要翻译：固体电解质电容器体嵌入在电绝缘树脂块中。每个连接到电容器主体的各个电极的输出端子从块突出。一个输出端子包括固定到一个电极的第一部分和与第一部分和电容器主体电绝缘的第二部分。独立的可熔部件建立第一和第二部分之间的电连接。易熔件嵌入刚性绝热树脂中，其在第一和第二部分之间延伸，以将它们机械连接在一起。

10. 发明授权

US4823236A High temperature aluminum electrolytic capacitor 失效
标题翻译：高温铝电解电容器
公开(公告)号：US4823236A
公开(公告)日：1989-04-18
申请号：US201000
申请日：1988-05-23
申请人： E. James Fresia
发明人： E. James Fresia
IPC分类号： H01G9/02 , H01G9/022
CPC分类号： H01G9/022
摘要： A capacitor having a wound aluminum foil electrolytic capacitor section contains an electrolyte solution of 10 to 32 wt % diethylammonium fumarate, 10 to 30 wt % N-methylpyrrolidinone, 4 to 7 wt % water, 0.1 to 0.5 wt % ammonium dihydrogen phosphate, with the remainder ethylene glycol. The capacitor is capable of operation at temperatures up to 125.degree. C.
摘要翻译：具有卷绕的铝箔电解电容器部的电容器含有10〜32重量％的富马酸二乙酯，10〜30重量％的N-甲基吡咯烷酮，4〜7重量％的水，0.1〜0.5重量％的磷酸二氢铵的电解液，剩余的乙二醇。该电容器能够在高达125℃的温度下运行。

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