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1. 发明授权

US11415622B2 Automated testing machine with data processing function and information processing method thereof 有权
公开(公告)号：US11415622B2
公开(公告)日：2022-08-16
申请号：US17083336
申请日：2020-10-29
申请人： SPIROX CORPORATION
发明人： Hsing-Fu Lin
IPC分类号： G01R31/28 , G01R31/319 , G01R31/317 , G01R31/3193
摘要： An automated testing machine with data processing function and an information processing method thereof are introduced. The automated testing machine includes a test head for testing more than one device under testing (DUT), and the test head further includes a test processing unit for providing more than one electrical test signal to the DUTs and conducting a processing and analyzing on more than one electrical feedback data fed back from the DUTs, so as to generate analysis result information. With the test processing unit capable of conducting data processing directly provided in the test head, signals obtained from the DUTs can be directly analyzed and processed to enable increased data processing efficiency, increased convenience in use and reduced costs of the automated test machine and the information processing method thereof.

2. 发明授权

US06906651B2 Constant current source with threshold voltage and channel length modulation compensation 失效
标题翻译：具有阈值电压和通道长度调制补偿的恒流源
公开(公告)号：US06906651B2
公开(公告)日：2005-06-14
申请号：US10758841
申请日：2004-01-16
申请人： Ching Hsiang Yang , Chun Wei Lin
发明人： Ching Hsiang Yang , Chun Wei Lin
IPC分类号： G05F3/26 , H03K17/041 , H03M1/66
CPC分类号： G05F3/262 , H03K17/04106
摘要： A constant current source with threshold voltage and channel length modulation includes first, second, third, fourth and fifth MOS transistors. Each of the MOS transistors has gate, first and second terminals. The first terminal of the second MOS transistor is coupled to loading impedance, and its second terminal is coupled with the first terminal of the first MOS transistor. The gate terminal and first terminal of the third MOS transistor are together coupled to the gate terminal of the second MOS transistor, and its second terminal is coupled to the first terminal of the fourth MOS transistor. The gate terminal and first terminal of the fourth MOS transistor are coupled to the gate terminal of the first MOS transistor, and its second terminal is coupled to a first reference voltage. The gate terminal and second terminal of the fifth MOS transistor are respectively coupled to a second reference voltage and a third reference voltage, and its first terminal is coupled to the gate terminal and first terminal of the third MOS transistor.
摘要翻译：具有阈值电压和沟道长度调制的恒流源包括第一，第二，第三，第四和第五MOS晶体管。每个MOS晶体管具有栅极，第一和第二端子。第二MOS晶体管的第一端子耦合到负载阻抗，并且其第二端子与第一MOS晶体管的第一端子耦合。第三MOS晶体管的栅极端子和第一端子一起耦合到第二MOS晶体管的栅极端子，并且其第二端子耦合到第四MOS晶体管的第一端子。第四MOS晶体管的栅极端子和第一端子耦合到第一MOS晶体管的栅极端子，并且其第二端子耦合到第一参考电压。第五MOS晶体管的栅极端子和第二端子分别耦合到第二参考电压和第三参考电压，并且其第一端子耦合到第三MOS晶体管的栅极端子和第一端子。

3. 发明授权

US07065689B2 Diagonal testing method for flash memories 失效
标题翻译：闪存对角线测试方法
公开(公告)号：US07065689B2
公开(公告)日：2006-06-20
申请号：US10602377
申请日：2003-06-24
申请人： Sau-Kwo Chiu , Jen-Chieh Yeh , Kuo-Liang Cheng , Chih-Tsun Huang , Cheng-Wen Wu
发明人： Sau-Kwo Chiu , Jen-Chieh Yeh , Kuo-Liang Cheng , Chih-Tsun Huang , Cheng-Wen Wu
IPC分类号： G11C29/00 , G11C7/00 , G06F12/16
CPC分类号： G11C29/10 , G11C16/04
摘要： The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in −45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.
摘要翻译：本发明公开了一种闪存的对角线测试方法。测试方法将闪存存储为几个方格，并从上到下，从左到右的方向执行。每个正方形设有从左上到右下的-45度的第一个对角线，以及从左下到右上的+45度的第二个对角线。本发明是对第一对角线或第二对角线中的单元进行编程，然后读取第一对角线或第二对角线以外的单元; 或者，对第一对角线或第二对角线以外的单元进行编程，然后读取第一对角线或第二对角线中的单元，以便检测闪速存储器和正常存储器故障模型中的干扰故障。

4. 发明申请

US20220099729A1 AUTOMATED TESTING MACHINE WITH DATA PROCESSING FUNCTION AND INFORMATION PROCESSING METHOD THEREOF 有权
公开(公告)号：US20220099729A1
公开(公告)日：2022-03-31
申请号：US17083336
申请日：2020-10-29
申请人： SPIROX CORPORATION
发明人： HSING-FU LIN
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193 , G01R31/317
摘要： An automated testing machine with data processing function and an information processing method thereof are introduced. The automated testing machine includes a test head for testing more than one device under testing (DUT), and the test head further includes a test processing unit for providing more than one electrical test signal to the DUTs and conducting a processing and analyzing on more than one electrical feedback data fed back from the DUTs, so as to generate analysis result information. With the test processing unit capable of conducting data processing directly provided in the test head, signals obtained from the DUTs can be directly analyzed and processed to enable increased data processing efficiency, increased convenience in use and reduced costs of the automated test machine and the information processing method thereof.

5. 发明授权

US07355537B2 Built-in self-test apparatus and method for digital-to-analog converter 失效
标题翻译：用于数模转换器的内置自检装置和方法
公开(公告)号：US07355537B2
公开(公告)日：2008-04-08
申请号：US10910342
申请日：2004-08-04
申请人： Chun Wei Lin
发明人： Chun Wei Lin
IPC分类号： H03M1/10
CPC分类号： G01R31/3187 , G01R31/3167 , H03M1/1095 , H03M1/66
摘要： A built-in self-test apparatus for a digital-to-analog converter uses a differentiation unit for differentiating a digital-to-analog (DA) signal to obtain the differences between pulses of the analog signal. Next, the analog signal is converted into a digital signal in the light of a threshold voltage by a Schmitt trigger unit. Then, the duty cycles of the digital signal are calculated by a duty cycle retriever, and transmitted into a signature analyzer to calculate the differential non-linearity for error analysis. For processing a high-speed DA signal, the circuit disposed before the differentiation unit may use a test pattern unit, a sample-and-hold circuit and a logic circuit to lower the speed of the DA signal.
摘要翻译：用于数模转换器的内置自检装置使用微分单元来区分数模（DA）信号以获得模拟信号的脉冲之间的差异。接下来，模拟信号通过施密特触发器单元根据阈值电压被转换为数字信号。然后，数字信号的占空比由占空比检索器计算，并发送到签名分析器中以计算误差分析的差分非线性。为了处理高速DA信号，设置在差分单元之前的电路可以使用测试图案单元，采样保持电路和逻辑电路来降低DA信号的速度。

6. 发明授权

US07015846B2 Constant current source with threshold voltage and channel length modulation compensation 失效
标题翻译：具有阈值电压和通道长度调制补偿的恒流源
公开(公告)号：US07015846B2
公开(公告)日：2006-03-21
申请号：US10919372
申请日：2004-08-17
申请人： Chun Wei Lin
发明人： Chun Wei Lin
IPC分类号： G05F3/16
CPC分类号： G05F3/267
摘要： A constant current source with threshold voltage and channel length modulation comprises a set of cascade transistors and a compensation circuit electrically connected to the set of cascade transistors so as to form a feedback circuit, in which the set of cascade transistors including a first MOS transistor and a second MOS transistor, and the compensation circuit comprises a third MOS transistor, a fourth MOS transistor, a sixth MOS transistor and a seventh MOS transistor. The gate terminal of the third MOS transistor is connected to the gate terminal of the second MOS transistor. The fourth MOS transistor is connected to the third MOS transistor in serial, and the gate terminal of the fourth MOS transistor is connected to the gate terminal of the first MOS transistor, and the second terminal of the fourth MOS transistor is connected to a current-supplying circuit. The gate terminals of the sixth and seventh MOS transistors are electrically connected to the current-supplying circuit, and a current is generated by mirroring flows through the third MOS transistor.
摘要翻译：具有阈值电压和沟道长度调制的恒流源包括一组级联晶体管和与该组级联晶体管电连接的补偿电路，以便形成反馈电路，其中该组级联晶体管包括第一MOS晶体管和第二MOS晶体管，并且所述补偿电路包括第三MOS晶体管，第四MOS晶体管，第六MOS晶体管和第七MOS晶体管。第三MOS晶体管的栅极端子连接到第二MOS晶体管的栅极端子。第四MOS晶体管串联连接到第三MOS晶体管，第四MOS晶体管的栅极端子连接到第一MOS晶体管的栅极端子，第四MOS晶体管的第二端子连接到电流 - 供电电路。第六和第七MOS晶体管的栅极端子电连接到电流供应电路，并且通过镜像流过第三MOS晶体管产生电流。

7. 发明授权

US06987472B2 Built-in-self-test apparatus and method for analog-to-digital converter 失效
标题翻译：用于模数转换器的内置自检装置和方法
公开(公告)号：US06987472B2
公开(公告)日：2006-01-17
申请号：US10912179
申请日：2004-08-06
申请人： Chun Wei Lin
发明人： Chun Wei Lin
IPC分类号： H03M1/10 , G06F101/14 , G06F15/00 , G06F17/18
CPC分类号： H03M1/109 , H03M1/12
摘要： A built-in-self-test apparatus for an analog-to-digital converter includes a digital-to-analog converter, a low-pass filter, a histogram analyzer and a software engine. The digital-to-analog converter is intended to generate a first signal. The low-pass filter is intended to smoothen the first signal so that an analog-to-digital converter can perform sampling on the smoothened first signal by a second signal, wherein the bit number of the second signal is greater than or equal to that of the first signal, and the frequency of the second signal is a multiple of that of the first signal. The histogram analyzer is electrically connected to the output end of the analog-to-digital converter. The software engine is electrically connected to the output end of the histogram analyzer so as to display the characteristics of the analog-to-digital converter.
摘要翻译：用于模数转换器的内置自检装置包括数模转换器，低通滤波器，直方图分析器和软件引擎。数模转换器旨在产生第一信号。低通滤波器旨在平滑第一信号，使得模数转换器可以通过第二信号对平滑的第一信号执行采样，其中第二信号的位数大于或等于第一信号，第二信号的频率是第一信号的倍数。直方图分析仪电连接到模数转换器的输出端。软件引擎电连接到直方图分析仪的输出端，以显示模数转换器的特性。

8. 发明申请

US20060126714A1 Method and apparatus for measuring signal jitters 审中-公开
标题翻译：用于测量信号抖动的方法和装置
公开(公告)号：US20060126714A1
公开(公告)日：2006-06-15
申请号：US11293117
申请日：2005-12-05
申请人： Chun Lin , Huo Chen , Raymond Chen
发明人： Chun Lin , Huo Chen , Raymond Chen
IPC分类号： H04B17/00
CPC分类号： H04L1/205
摘要： A measuring method for signal jitter comprises the following procedures: First, a first data signal is provided, and the first data signal is deemed equivalent to a second data signal, wherein frequency of the first data signal is a multiple (preferably odd) of that of the second data signal, and at the same time, the ascent and the descent edges of the second data signal are the same as that of the first data signal. The widths of the high and low levels of the second data signal are counted so as to generate an estimated jitter stream including the estimated jitter values of the ascent and the descent edges of the second data signal. Then, jitter distribution diagrams of the ascent and the descent edges are established based on the estimated jitter stream, so as to calculate an eye open (EO) value.
摘要翻译：用于信号抖动的测量方法包括以下步骤：首先，提供第一数据信号，并且将第一数据信号视为等同于第二数据信号，其中第一数据信号的频率是该数字信号的倍数（优选奇数）的第二数据信号，并且同时第二数据信号的上升沿和下降沿与第一数据信号的上升沿和下降沿相同。对第二数据信号的高电平和低电平的宽度进行计数，以产生包括第二数据信号的上升和下降沿的估计抖动值的估计抖动流。然后，基于估计的抖动流建立上升沿和下降沿的抖动分布图，以计算眼图（EO）值。

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