专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5818832A Rapid synchronization for communication systems 失效
标题翻译：通讯系统快速同步
公开(公告)号：US5818832A
公开(公告)日：1998-10-06
申请号：US740016
申请日：1996-10-23
申请人： Ronald D. McCallister
发明人： Ronald D. McCallister
IPC分类号： H04W4/06 , H04W28/22 , H04W72/04 , H04W74/04 , H04W84/14 , H04W99/00 , H04L27/06
CPC分类号： H04L5/1446 , H04L5/1453 , H04W28/22 , H04W56/0035 , H04W84/14 , H04W4/06 , H04W48/08 , H04W48/16 , H04W72/0446 , H04W74/04
摘要： A local multipoint data distribution system (10) simultaneously accommodates many communication sessions occurring at a variety of data rates. Space surrounding cell sites (12) is partitioned into sectors (16), and the spectrum is allocated so that adjacent sectors (16) use different spectrum portions, but the entire spectrum is reused numerous times. A time diversity scheme allocates different numbers of time slots (54) to different calls. Time slot identifiers are assigned in contiguous blocks in an assigned numbering system (56). The time slot identifier assignments are translated into a counted numbering system (58) which causes the time slots (54) for any call to be distributed throughout a frame (48) and interleaved with time slots (54) assigned to other calls. Data communications use a common modulation format and a modulation order that is specifically adapted to a particular call. A spectral coherence technique causes reverse channel signal (158) to be transmitted at a frequency to which a base station demodulator (170) is already synchronized.
摘要翻译：本地多点数据分发系统（10）同时容纳以各种数据速率发生的许多通信会话。空间周围的小区站点（12）被划分为扇区（16），并且分配频谱使得相邻扇区（16）使用不同的频谱部分，但是整个频谱被重复使用多次。时间分集方案将不同数量的时隙（54）分配给不同的呼叫。在分配的编号系统（56）中的连续块中分配时隙标识符。时隙标识符分配被转换成计数的编号系统（58），其使得任何呼叫的时隙（54）分布在整个帧（48）中并与分配给其他呼叫的时隙（54）进行交织。数据通信使用普通调制格式和专门适用于特定呼叫的调制顺序。频谱相干技术使得反向信道信号（158）以基站解调器（170）已经同步的频率被发送。

2. 发明授权

US5440265A Differential/coherent digital demodulator operating at multiple symbol points 失效
标题翻译：差分/相干数字解调器在多个符号点运行
公开(公告)号：US5440265A
公开(公告)日：1995-08-08
申请号：US306112
申请日：1994-09-14
申请人： Bruce A. Cochran , Ronald D. McCallister , Brendan J. Garvey
发明人： Bruce A. Cochran , Ronald D. McCallister , Brendan J. Garvey
IPC分类号： H04L1/00 , H04L1/20 , H04L7/04 , H04L27/22 , H04L27/14
CPC分类号： H04L1/0059 , H04L1/20 , H04L27/22 , H04L7/046
摘要： Symbols (18) of a burst (12) are sub-divided into symbol sections (20). Each symbol section (20) is sampled and converted into polar coordinates. A buffer bank (38) selectably delays the samples and replays a preamble (14). A demod bank (40) includes a coherent demod (58) and several differential demods (60). Each differential demod (60) processes its own stream of symbol sections (20). The differential demods (60) feed a preamble detector (66) and a symbol synchronization circuit (62). The symbol synchronization circuit (62) identifies the symbol section (20) which yields the smallest magnitude of frequency errors. This symbol section (20) is processed by the coherent demod (58) to acquire carrier phase and recover data. The coherent demod (58) is implemented in the phase domain so that only oscillation signal phase data need be generated in phase locked loops. Two phase locked loops (110, 112) operate in parallel but with initial reference phase offsets so that at least one of the two loops will not experience hang-up.
摘要翻译：突发（12）的符号（18）被细分为符号部分（20）。每个符号部分（20）被采样并转换成极坐标。缓冲器组（38）可选地延迟样本并重播前导码（14）。解调块（40）包括相干解调（58）和几个差分解调（60）。每个差分解调器（60）处理它自己的符号段（20）流。差分解调器（60）馈送前导码检测器（66）和符号同步电路（62）。符号同步电路（62）识别产生最小频率误差幅度的符号部分（20）。该符号部分（20）由相干解调（58）处理以获取载波相位并恢复数据。相位解调（58）在相位域中实现，使得只需要在锁相环中产生振荡信号相位数据。两个锁相环（110,112）并联操作，但具有初始参考相位偏移，使得两个回路中的至少一个不会经历挂起。

3. 发明授权

US6128282A Network node controller and method for combining circuit and packet data 失效
标题翻译：网络节点控制器和组合电路和数据包数据的方法
公开(公告)号：US6128282A
公开(公告)日：2000-10-03
申请号：US994002
申请日：1997-12-18
申请人： John M. Liebetreu , Ronald D. McCallister
发明人： John M. Liebetreu , Ronald D. McCallister
IPC分类号： H04L12/56 , H04Q11/04 , H04J3/24 , H04J3/00 , H04L12/66
CPC分类号： H04Q11/0478 , H04L2012/5612
摘要： A node controller (30) within a data communication network (22) provides network access for a digital data stream (32). A processor (42) partitions the digital data stream (32) into a constant data rate component (44) having a predictable data rate and a data packet component (46) having an unpredictable data rate. The constant data rate component (44) is then transferred over a first portion (74) of a network data stream (26) reserved for a circuit transmission protocol, and the data packet component (46) is packetized and transferred over a second portion (76) of the network data stream (26) reserved for a packet transmission protocol.
摘要翻译：数据通信网络（22）内的节点控制器（30）为数字数据流（32）提供网络接入。处理器（42）将数字数据流（32）分割成具有可预测数据速率的恒定数据速率分量（44）和具有不可预测数据速率的数据分组分量（46）。恒定数据速率分量（44）然后通过为电路传输协议保留的网络数据流（26）的第一部分（74）传送，并且数据分组组件（46）被分组化并在第二部分 76）被保留用于分组传输协议的网络数据流（26）。

4. 发明授权

US5910967A Pragmatic encoder and method therefor 失效
标题翻译：语用编码器及其方法
公开(公告)号：US5910967A
公开(公告)日：1999-06-08
申请号：US954550
申请日：1997-10-20
申请人： Mark J. Vanderaar
发明人： Mark J. Vanderaar
IPC分类号： H03M13/23 , H03M13/25 , H03M13/29 , H04L1/00 , H04L27/18 , H04L5/12 , H03M13/12
CPC分类号： H04L1/0057 , H03M13/23 , H03M13/253 , H03M13/256 , H03M13/2933 , H03M13/333 , H04L1/006 , H04L1/0065 , H04L1/0071 , H04L27/186
摘要： A communication system (11) uses concatenated coding in which an inner code is configured to match the needs of an outer code. The inner code is implemented through a pragmatic trellis coded modulation encoder (18) and decoder (34). A parser (50) of the encoder (18) distributes fewer than one user information bit per unit interval (66) to a convolutional encoder (58) which generates at least two convolutionally encoded bits for each user information bit it processes. Exactly one of the convolutionally encoded bits is phase mapped (56) with at least two user information bits during each unit interval (66). The decoder (34) detects a frame sync pattern (48) inserted into the user information bits to resolve phase ambiguities. Phase estimates are convolutionally decoded (100) to provide decoded data estimates that are then used to selectively rotate the phase estimates prior to routing the phase estimates to a slice detector (118).
摘要翻译：通信系统（11）使用连接编码，其中内部码被配置为匹配外部码的需要。内部代码通过实用的网格编码调制编码器（18）和解码器（34）来实现。编码器（18）的解析器（50）将每单位间隔（66）的不到一个用户信息比特分配到卷积编码器（58），该卷积编码器（58）为其处理的每个用户信息比特生成至少两个卷积编码比特。在每个单位间隔（66）期间，具有至少两个用户信息比特的卷积编码比特中的一个完全相位映射（56）。解码器（34）检测插入到用户信息位中的帧同步模式（48）以解决相位模糊。相位估计被卷积解码（100）以提供解码的数据估计，然后在将相位估计路由到切片检测器（118）之前，将其用于选择性地旋转相位估计。

5. 发明授权

US5671257A Symbol timing recovery based on complex sample magnitude 失效
标题翻译：基于复杂采样幅度的符号定时恢复
公开(公告)号：US5671257A
公开(公告)日：1997-09-23
申请号：US468921
申请日：1995-06-06
申请人： Bruce A. Cochran , Ronald D. McCallister
发明人： Bruce A. Cochran , Ronald D. McCallister
IPC分类号： H03L7/087 , H03L7/091 , H04L7/00 , H04L7/02 , H04L7/033
CPC分类号： H04L7/0054 , H03L7/087 , H04L7/0334 , H03L7/091 , H04L7/0083
摘要： A digital communication receiver (10) takes one complex sample (20) of a baseband analog signal (12) per symbol. A rectangular to polar converter (26) separates phase attributes of the complex samples from magnitude attributes. A phase processor (28) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (32) influences symbol timing only during clock adjustment opportunities. The magnitude processor (32) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities. An interpolator (66) may be used to estimate magnitude values between samples so that magnitude change is determined between sampled magnitude values and estimated magnitude values.
摘要翻译：数字通信接收机（10）每个符号采用基带模拟信号（12）的一个复样本（20）。矩形到极化转换器（26）将复数样本的相位属性与幅度属性分开。相位处理器（28）识别在相邻符号之间发生相对大的相位变化时发生的时钟调整机会。幅度处理器（32）仅在时钟调整机会期间影响符号定时。当在时钟调整机会期间检测到减小的幅度变化时，幅度处理器（32）在锁相环中提前符号定时，并且在时钟调整机会期间检测到增加幅度变化时延迟符号定时。可以使用内插器（66）来估计样本之间的幅度值，使得在采样的幅度值和估计的幅度值之间确定幅度变化。

6. 发明授权

US6097764A Pragmatic trellis-coded modulation system and method therefor 失效
标题翻译：实用网格编码调制系统及其方法
公开(公告)号：US6097764A
公开(公告)日：2000-08-01
申请号：US48612
申请日：1998-03-26
申请人： Ronald D. McCallister , Bruce A. Cochran , John M. Liebetreu
发明人： Ronald D. McCallister , Bruce A. Cochran , John M. Liebetreu
IPC分类号： H03M13/25 , H03M13/29 , H03M13/41 , H04L1/00 , H04L27/00 , H04L27/34 , H04L27/38 , H03M13/12
CPC分类号： H04L1/006 , H03M13/253 , H03M13/256 , H03M13/2936 , H03M13/3776 , H03M13/3961 , H03M13/41 , H03M13/6325 , H03M13/6362 , H03M13/6508 , H04L1/0054 , H04L1/0065 , H04L1/0068 , H04L27/3416 , H04L27/3827 , H04L2027/003 , H04L2027/0055
摘要： A digital communication system (20) communicates using a polar amplitude phase shift keyed (P-APSK) phase point constellation (70, 70', 70"). Pragmatic encoding is accommodated using the constellation (70, 70', 70") to simultaneously communicate both encoded and uncoded information bits (69, 51). The constellation (70, 70', 70") has an even number of phase point rings (74) and equal numbers of phase points (72) in ring pairs (75, 76, 77). Encoded information bits (69) specify secondary modulation and uncoded information bits (51) specify primary modulation. The constellation (70, 70', 70") is configured so secondary sub-constellations (78) include four phase points (72) arranged so that two of the four phase points (72) exhibit two phase angles at one magnitude and the other two of the four phase points (72) exhibit phase angles that are at another magnitude. The difference between the phase angles at different magnitudes within a secondary sub-constellation (78) is constant.
摘要翻译：数字通信系统（20）使用极振幅相移键控（P-APSK）相位点星座（70,70'，70“）进行通信。使用星座（70,70'，70“）来容纳语音编码以同时传送编码和未编码的信息比特（69,51）。星座（70,70'，70“）具有环形对（75,76,77）中的偶数个相位点环（74）和相等数量的相位点（72）。编码信息位（69）指定二次调制和未编码信息位（51）指定一次调制。星座（70,70'，70“）被配置为使得次星座（78）包括四个相位点（72），四个相位点（72）布置成使四个相位点（72）中的两个呈现一个幅度的两个相位角，四个相位点（72）中的其他两个表现出处于另一个幅度的相位角。次级星座（78）内不同幅度的相位角之间的差异是恒定的。

7. 发明授权

US6078625A Pragmatic decoder and method therefor 失效
标题翻译：语用解码器及其方法
公开(公告)号：US6078625A
公开(公告)日：2000-06-20
申请号：US954762
申请日：1997-10-20
申请人： Ronald D. McCallister , Bruce A. Cochran , John M. Liebetreu
发明人： Ronald D. McCallister , Bruce A. Cochran , John M. Liebetreu
IPC分类号： H04L1/00 , H04L27/18 , H03D1/00
CPC分类号： H04L1/0065 , H04L1/0047 , H04L1/006 , H04L27/186 , H04L1/0054 , H04L1/0057
摘要： A communication system (11) uses concatenated coding in which an inner code is configured to match the needs of an outer code. The inner code is implemented through a pragmatic trellis coded modulation encoder (18) and decoder (34). A parser (50) of the encoder (18) distributes fewer than one user information bit per unit interval (66) to a convolutional encoder (58) which generates at least two convolutionally encoded bits for each user information bit it processes. Exactly one of the convolutionally encoded bits is phase mapped (56) with at least two user information bits during each unit interval (66). The decoder (34) detects a frame sync pattern (48) inserted into the user information bits to resolve phase ambiguities. Phase estimates are convolutionally decoded (100) to provide decoded data estimates that are then used to selectively rotate the phase estimates prior to routing the phase estimates to a slice detector (118).
摘要翻译：通信系统（11）使用连接编码，其中内部码被配置为匹配外部码的需要。内部代码通过实用的网格编码调制编码器（18）和解码器（34）来实现。编码器（18）的解析器（50）将每单位间隔（66）的不到一个用户信息比特分配到卷积编码器（58），该卷积编码器（58）为其处理的每个用户信息比特生成至少两个卷积编码比特。在每个单位间隔（66）期间，具有至少两个用户信息比特的卷积编码比特中的一个完全相位映射（56）。解码器（34）检测插入到用户信息位中的帧同步模式（48）以解决相位模糊。相位估计被卷积解码（100）以提供解码的数据估计，然后在将相位估计路由到切片检测器（118）之前，将其用于选择性地旋转相位估计。

8. 发明授权

US5774084A Method and apparatus for translating digital data into an analog signal 失效
标题翻译：将数字数据转换为模拟信号的方法和装置
公开(公告)号：US5774084A
公开(公告)日：1998-06-30
申请号：US627930
申请日：1996-04-03
申请人： Eric Martin Brombaugh , John Michael Liebetreu , Ronald Duane McCallister
发明人： Eric Martin Brombaugh , John Michael Liebetreu , Ronald Duane McCallister
IPC分类号： G06F1/025 , H03M1/82 , H03M1/66
CPC分类号： H03M1/827 , G06F1/025 , H03M1/825
摘要： A pulse width modulation (PWM) circuit translates digital data into an analog signal. The PWM circuit includes at least a digital counter, a significance reverser, and a comparator circuit. The significance reverser reverses the relative order of significance of at least two bits in the count words generated by the counter. The comparator determines whether the magnitude of a digital input word is greater than the magnitude of the reversed order count word. The PWM circuit produces a high output when the magnitude of the input word is greater than the magnitude of the reversed order count word and a low output when the magnitude of the input word is not greater than the magnitude of the reversed order count word. The analog output produced by the PWM circuit includes a number of pulses evenly distributed during the count cycle of the counter, and the input word indicates a duty cycle for the analog output. The PWM circuit includes a programmable output gain feature and an output interface that mimics the output configuration of conventional phase/frequency detector circuits.
摘要翻译：脉冲宽度调制（PWM）电路将数字数据转换为模拟信号。 PWM电路至少包括一个数字计数器，一个有效反向器和一个比较器电路。显着性反转器反转由计数器产生的计数字中至少两位的显着性的相对顺序。比较器确定数字输入字的大小是否大于反转顺序计数字的大小。当输入字的大小大于反相计数字的大小时，PWM电路产生高输出，而当输入字的大小不大于反转顺序计数字的大小时，PWM电路产生高输出。由PWM电路产生的模拟输出包括在计数器的计数周期期间均匀分布的脉冲数，输入字表示模拟输出的占空比。 PWM电路包括可编程输出增益特征和模拟常规相位/频率检测器电路的输出配置的输出接口。

9. 发明授权

US5386202A Data communication modulation with managed intersymbol interference 失效
标题翻译：数据通信调制与管理的符号间干扰
公开(公告)号：US5386202A
公开(公告)日：1995-01-31
申请号：US146925
申请日：1993-11-03
申请人： Bruce A. Cochran , Ronald D. McCallister
发明人： Bruce A. Cochran , Ronald D. McCallister
IPC分类号： H04L1/20 , H04L25/497 , H03C3/00 , H03D3/00 , H04L1/00 , H04L27/10
CPC分类号： H04L25/497 , H04L1/20
摘要： A communication system (10) includes a modulation section (12) and a demodulation section (14). The modulation section (12) performs frequency modulation in accordance with a frequency trajectory signal (28, 30, 32). An intersymbol interference (ISI) prediction filter (20) adjusts the amplitude of the frequency trajectory signal (28, 30, 32) in response to data code (16) sequences being conveyed over a plurality of symbols (18). More frequent data changes in the sequence of the data codes (16) lead to greater amplitudes in the frequency trajectory signal. The demodulation section (14) applies a distorted phase signal to a decision circuit (38). The distorted phase signal conveys a received phase (46) that includes ISI. Due to the equalization applied by the ISI prediction filter (20), the received phase (46) approximates a target phase (40, 42) in spite of the ISI.
摘要翻译：通信系统（10）包括调制部（12）和解调部（14）。调制部（12）根据频率轨迹信号（28,30,32）进行频率调制。符号间干扰（ISI）预测滤波器（20）响应于在多个符号（18）上传送的数据码（16）来调整频率轨迹信号（28,30,32）的振幅。数据码（16）序列中更频繁的数据变化导致频率轨迹信号的幅度更大。解调部（14）将失真的相位信号施加到判定电路（38）。失真的相位信号传送包括ISI的接收相位（46）。由于由ISI预测滤波器（20）施加的均衡，接收相位（46）尽管有ISI近似目标相位（40,42）。

10. 再颁专利

USRE41380E1 Constrained-envelope digital-communications transmission system and method therefor 有权
标题翻译：约束包络数字通信传输系统及其方法
公开(公告)号：USRE41380E1
公开(公告)日：2010-06-15
申请号：US10718507
申请日：2003-11-19
申请人： Ronald D. McCallister , Bruce A. Cochran , Bradley P. Badke
发明人： Ronald D. McCallister , Bruce A. Cochran , Bradley P. Badke
IPC分类号： H04K1/02 , H04L25/03 , H04L25/49
CPC分类号： H04L25/03834 , H04B1/717 , H04B1/719 , H04B2201/70706 , H04L27/2614 , H04L27/2627 , H04L27/3411 , H04L27/3494 , H04L27/363
摘要： A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies the constrained-envelope signal stream (112) and transmits it as a radio-frequency broadcast signal (26).
摘要翻译：一种限制包络数字通信发射机电路（22），其中二进制数据源（32）提供输入信号流（34），相位映射器（44）将输入信号流（34）映射到正交相位点信号流（50），每单位波特间隔（64）具有预定数量的符号，并且在相位点星座（46）中定义相位点（54），脉冲扩展滤波器（76）对相位点信号流（50）转换成经滤波的信号流（74），约束包络发生器（106）从经滤波的信号流（74）产生约束带宽误差信号流（108），延迟元件（138）信号流（74）转换成与受约束带宽误差信号流（108）同步的延迟信号流（140），复数求和电路（110）将延迟信号流（140）和约束带宽误差信号流 108）到约束包络信号流（112）中，并且基本上是线性的放大器（146）放大约束包络信号流（112）并将其作为射频广播信号（26）发送。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式