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1. 发明授权

US08097872B2 Modifiable gate stack memory element 有权
标题翻译：可修改的门堆栈存储元件
公开(公告)号：US08097872B2
公开(公告)日：2012-01-17
申请号：US11708664
申请日：2007-02-20
申请人： Franz Kreupl
发明人： Franz Kreupl
IPC分类号： H01L29/04
CPC分类号： H01L29/78 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/71 , H01L29/0673 , H01L29/42324 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/517 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/7887
摘要： An apparatus and method for storing information are provided, including using an integrated circuit including a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. To store information, the on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer.
摘要翻译：提供一种用于存储信息的装置和方法，包括使用包括具有通道的晶体管，栅极氧化物层，栅极电极和可修改栅极堆叠层的集成电路。为了存储信息，通过在可修改的栅极堆叠层中引起基于非电荷储存的物理变化来改变晶体管的导通电阻。

2. 发明授权

US07910210B2 Method of producing a layer arrangement, method of producing an electrical component, layer arrangement, and electrical component 有权
标题翻译：制造层布置的方法，制造电气部件的方法，层布置以及电气部件
公开(公告)号：US07910210B2
公开(公告)日：2011-03-22
申请号：US11602460
申请日：2006-11-20
申请人： Franz Kreupl , Maik Liebau , Georg Duesberg , Christian Kapteyn
发明人： Franz Kreupl , Maik Liebau , Georg Duesberg , Christian Kapteyn
IPC分类号： B32B9/00 , C23C16/00
CPC分类号： H01L23/53276 , C23C16/26 , C23C16/32 , H01L21/3146 , H01L21/3148 , H01L21/32051 , H01L21/76834 , H01L21/76838 , H01L23/5223 , H01L2924/0002 , Y10T428/30 , H01L2924/00
摘要： In a method of producing a layer arrangement, a substantially carbon-comprising, electrically conductive carbon layer is formed. A protective layer is formed on the carbon layer. An electrically insulating layer is formed on the protective layer, the protective layer protecting the carbon layer from damage during the formation of the electrically insulating layer. Furthermore, a layer arrangement is provided, having a substantially carbon-comprising, electrically conductive carbon layer, a protective layer formed on the carbon layer, and an electrically insulating layer formed on the protective layer, the protective layer being used to avoid damage to the carbon layer by the electrically insulating layer.
摘要翻译：在制备层布置的方法中，形成基本上含碳的导电碳层。在碳层上形成保护层。在保护层上形成电绝缘层，保护层在形成电绝缘层期间保护碳层免受损坏。此外，提供了一种层布置，其具有基本上包含碳的导电碳层，形成在碳层上的保护层，以及形成在保护层上的电绝缘层，保护层用于避免损坏碳层由电绝缘层。

3. 发明授权

US07881092B2 Increased switching cycle resistive memory element 有权
标题翻译：增加开关周期电阻性存储元件
公开(公告)号：US07881092B2
公开(公告)日：2011-02-01
申请号：US11782525
申请日：2007-07-24
申请人： Klaus Ufert
发明人： Klaus Ufert
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C13/0004 , G11C13/0011 , G11C2213/32 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： An integrated circuit including a resistive memory element and a method of manufacturing the integrated circuit are described. The method of manufacturing the integrated circuit includes depositing a switching layer material and intentionally forming inhomogeneously distributed defects within the switching layer material to increase a number of switching cycles of the resistive memory element. The resistive memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state. The switching layer contains intentionally formed defects that increase the number of switching cycles of the switching layer.
摘要翻译：描述了包括电阻性存储元件的集成电路和制造集成电路的方法。集成电路的制造方法包括沉积切换层材料并有意在开关层材料内形成非均匀分布的缺陷以增加电阻式存储元件的开关次数。电阻性存储元件包括选择性地在低电阻状态和高电阻状态之间切换的开关层。开关层包含有意形成的缺陷，其增加了开关层的开关周期数。

4. 发明授权

US07701743B2 Electronic circuit package 失效
标题翻译：电子电路封装
公开(公告)号：US07701743B2
公开(公告)日：2010-04-20
申请号：US12222329
申请日：2008-08-07
申请人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
发明人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
IPC分类号： G11C5/06
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
摘要翻译：一种电子设备，其包括布线基板和布线基板上形成的多个半导体裸芯片。半导体裸芯片包括用于处理数据的处理器和具有用于检测处理器的故障的检查功能的电路。

5. 再颁专利

USRE41379E1 Large-Capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed 有权
标题翻译：大容量半导体存储器，具有改进的子放大器布局以提高操作速度
公开(公告)号：USRE41379E1
公开(公告)日：2010-06-15
申请号：US11759345
申请日：2007-06-07
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

6. 发明授权

US07688670B2 Semiconductor device with improved power supply control for a plurality of memory arrays 有权
标题翻译：具有用于多个存储器阵列的改进的电源控制的半导体器件
公开(公告)号：US07688670B2
公开(公告)日：2010-03-30
申请号：US12165681
申请日：2008-07-01
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要翻译：提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。然而，第二电源电路在掉电模式期间连续运行。在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

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