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1. 发明授权

US08779495B2 Stacked SONOS memory 失效
标题翻译：堆叠SONOS内存
公开(公告)号：US08779495B2
公开(公告)日：2014-07-15
申请号：US11737531
申请日：2007-04-19
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , G11C16/0483 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/785
摘要： An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.
摘要翻译：集成电路包括第一SONOS存储单元和第二SONOS存储单元。第二存储单元堆叠在第一存储单元上。

2. 发明授权

US08665629B2 Condensed memory cell structure using a FinFET 有权
标题翻译：使用FinFET的冷凝存储单元结构
公开(公告)号：US08665629B2
公开(公告)日：2014-03-04
申请号：US11864575
申请日：2007-09-28
申请人： Human Park , Ulrich Klostermann , Rainer Leuschner
发明人： Human Park , Ulrich Klostermann , Rainer Leuschner
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , H01L27/2436 , H01L29/66795 , H01L29/785
摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.
摘要翻译：对集成电路的集成电路及其制造方法进行说明。在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于翅片结构的高度。

3. 发明授权

US08637844B2 Method for fabrication of crystalline diodes for resistive memories 有权
标题翻译：制造电阻式存储器晶体二极管的方法
公开(公告)号：US08637844B2
公开(公告)日：2014-01-28
申请号：US13097307
申请日：2011-04-29
申请人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
发明人： Bipin Rajendran , Thomas Happ , Hsiang-Lan Lung , Min Yang
IPC分类号： H01L47/00
CPC分类号： H01L27/24 , H01L21/02532 , H01L21/0262 , H01L21/02645 , H01L21/02667 , H01L27/1021 , H01L29/8613
摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
摘要翻译：本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

4. 发明授权

US08633053B2 Photovoltaic device 失效
标题翻译：光伏装置
公开(公告)号：US08633053B2
公开(公告)日：2014-01-21
申请号：US12638674
申请日：2009-12-15
申请人： Martin Detje , Iris Maege , Lars Voelkel
发明人： Martin Detje , Iris Maege , Lars Voelkel
IPC分类号： H01L31/18 , H01L31/042 , H01L31/0236
CPC分类号： H01L31/02168 , G02B1/111 , Y02E10/50
摘要： A photovoltaic device is described. The photovoltaic device comprises an organic-based antireflection layer. A method of making a photovoltaic device is also described.
摘要翻译：描述光伏器件。光伏器件包括有机基抗反射层。还描述了制造光伏器件的方法。

5. 发明授权

US08629575B2 Integrated circuit and method for charge reversal of a circuit part of the integrated circuit 有权
标题翻译：用于集成电路电路部分的电荷反转的集成电路和方法
公开(公告)号：US08629575B2
公开(公告)日：2014-01-14
申请号：US12168747
申请日：2008-07-07
申请人： Harald Roth , Helmut Schneider
发明人： Harald Roth , Helmut Schneider
IPC分类号： H02J1/00
CPC分类号： G11C8/08 , G11C11/4085 , Y10T307/675
摘要： A description is given of a method for charge reversal of a circuit part of an integrated circuit from a first electrical potential to a second electrical potential of a first voltage network. In this case, the circuit part is connected to the first voltage network for charge reversal. Furthermore, the circuit part is connected to a second voltage network for charge reversal, said second voltage network providing a third electrical potential between the first and the second electrical potential. The circuit part is automatically isolated from the second voltage network before its electrical potential reaches the second electrical potential.
摘要翻译：给出了对集成电路的电路部分从第一电压网络的第一电位到第二电位的电荷反转的方法的描述。在这种情况下，电路部分连接到第一电压网络进行充电反转。此外，电路部分连接到用于电荷反向的第二电压网络，所述第二电压网络在第一和第二电位之间提供第三电位。电路部分在其电位达到第二电位之前自动与第二电压网络隔离。

6. 发明授权

US08618600B2 Integrated circuit including a buried wiring line 有权
标题翻译：集成电路包括埋地布线
公开(公告)号：US08618600B2
公开(公告)日：2013-12-31
申请号：US12135318
申请日：2008-06-09
申请人： Stafan Slesazeck
发明人： Stafan Slesazeck
IPC分类号： H01L29/66
CPC分类号： H01L21/823437 , H01L21/743 , H01L21/823475 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area.
摘要翻译：集成电路包括埋地布线留置。一个实施例提供一种场效应晶体管，其包括掩埋在半导体衬底主表面下方的第一有源区和栅电极。栅极布线可以埋在主表面下方，并且栅极布线的一部分可以形成栅电极。在栅极布线之上，形成与第一或第二有源区域相邻且直接接触的埋入接触结构。

7. 发明授权

US08606982B2 Derivative logical output 失效
标题翻译：微分逻辑输出
公开(公告)号：US08606982B2
公开(公告)日：2013-12-10
申请号：US12045369
申请日：2008-03-10
申请人： Michael Maldei , Petra Stumm
发明人： Michael Maldei , Petra Stumm
IPC分类号： G06F13/14
CPC分类号： G06F13/4217 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention are related to methods, systems, and articles of manufacture for transferring data between two devices using an interconnect bus. On each conductive line of the bus, a bit representing a first logic state is transferred if a current bit is the same as an immediately previously transmitted bit. If the current bit is different from the immediately previously transmitted bit, then a bit representing a second logic state is transferred.
摘要翻译：本发明的实施例涉及使用互连总线在两个设备之间传送数据的方法，系统和制品。在总线的每个导线上，如果当前位与之前发送的位相同，则传送表示第一逻辑状态的位。如果当前位不同于紧接在先发送的位，则传送表示第二逻辑状态的位。

8. 发明授权

US08598716B2 Semiconductor apparatus having stacked semiconductor components 失效
标题翻译：半导体装置具有堆叠的半导体元件
公开(公告)号：US08598716B2
公开(公告)日：2013-12-03
申请号：US11210723
申请日：2005-08-24
申请人： Harry Hedler , Roland Irsigler , Thorsten Meyer
发明人： Harry Hedler , Roland Irsigler , Thorsten Meyer
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06586 , H01L2924/01078 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： The present invention provides an apparatus having stacked semiconductor components. Two semiconductor components (21, 26) are arranged such that their contact regions (28, 22) are opposite one another. A contact-connection device (29) forms a short electrical connection between the two contact regions (28, 22). The contact regions (28, 22) are connected to external contact regions (36) of the apparatus via a rewiring (23).
摘要翻译：本发明提供一种具有层叠半导体元件的装置。两个半导体部件（21,26）被布置成使得它们的接触区域（28,22）彼此相对。接触连接装置（29）在两个接触区域（28,22）之间形成短路电连接。接触区域（28,22）经由重新布线（23）连接到设备的外部接触区域（36）。

9. 发明授权

US08595449B2 Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition 有权
标题翻译：用于响应于触发条件来管理电阻性存储器中的维护操作的存储器调度器
公开(公告)号：US08595449B2
公开(公告)日：2013-11-26
申请号：US12202581
申请日：2008-09-02
申请人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
发明人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C13/00 , G11C11/00 , G11C11/34 , G11C16/06 , G11C16/04 , G11C7/04
CPC分类号： G11C7/04 , G11C13/0002 , G11C13/0033 , G11C16/3431
摘要： An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.
摘要翻译：集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。内存调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

10. 发明授权

US08384062B2 Memory including vertical bipolar select device and resistive memory element 失效
标题翻译：存储器包括垂直双极选择器件和电阻存储元件
公开(公告)号：US08384062B2
公开(公告)日：2013-02-26
申请号：US12853791
申请日：2010-08-10
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： H01L21/82
CPC分类号： H01L27/2463 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148
摘要： A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.
摘要翻译：存储器包括包括第一基极和第一发射极的第一垂直双极选择器件，耦合到第一发射极的第一相变元件，包括第二基极和第二发射极的第二垂直双极选择器件，第二相变元件耦合并且与第一基底和第二基底接触的掩埋字线。

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