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    • 1. 发明授权
    • Transient voltage suppression device
    • 瞬态电压抑制装置
    • US06867436B1
    • 2005-03-15
    • US10635088
    • 2003-08-05
    • Fred MattesonVenkatesh Panemangalore PaiDonald K. Cartmell
    • Fred MattesonVenkatesh Panemangalore PaiDonald K. Cartmell
    • H01L27/08H01L29/861H01L29/866H01L29/30H01L29/88H01L31/107
    • H01L27/0814H01L27/0817H01L29/861H01L29/866
    • A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage. The TVS device is packaged as a flip chip (202) that has four solder bump pads (211-214). The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
    • 双向瞬态电压抑制(“TVS”)器件(101)包括半导体管芯(201),其具有与阴极 - 阴极连接的第一整流二极管(104)串联的第一雪崩二极管(103) 具有与第二整流二极管(106)串联的第二雪崩二极管(105)的反并联配置也连接阴极至阴极。 TVS器件的所有二极管都在单个半导体衬底(301)上。 芯片具有设置在具有相反导电类型的半导体衬底(301)和具有第一导电类型的高电阻率外延层(305)之间的具有第一导电类型的低电阻率掩埋扩散层(303)。 掩埋扩散层将大部分瞬态电流从第一雪崩二极管和第一整流二极管之间的外延层的一部分分流,从而相对于击穿电压降低钳位电压。 TVS装置被封装成具有四个焊料凸块(211-214)的倒装芯片(202)。 提交摘要的理解是,根据37 C.F.R.不会将其用于解释或限制权利要求的范围或含义。 §1.72(b)。
    • 2. 发明授权
    • Transient voltage suppression device
    • 瞬态电压抑制装置
    • US07510903B1
    • 2009-03-31
    • US12042826
    • 2008-03-05
    • Fred MattesonVenkatesh P. PaiDonald K. Cartmell
    • Fred MattesonVenkatesh P. PaiDonald K. Cartmell
    • H01L21/00H01L21/20
    • H01L27/0814H01L27/0817H01L29/861H01L29/866
    • A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage. The TVS device is packaged as a flip chip (202) that has four solder bump pads (211-214). The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
    • 双向瞬态电压抑制(“TVS”)器件(101)包括半导体管芯(201),其具有与阴极 - 阴极连接的第一整流二极管(104)串联的第一雪崩二极管(103) 具有与第二整流二极管(106)串联的第二雪崩二极管(105)的反并联配置也连接阴极至阴极。 TVS器件的所有二极管都在单个半导体衬底(301)上。 芯片具有设置在具有相反导电类型的半导体衬底(301)和具有第一导电类型的高电阻率外延层(305)之间的具有第一导电类型的低电阻率掩埋扩散层(303)。 掩埋扩散层将大部分瞬态电流从第一雪崩二极管和第一整流二极管之间的外延层的一部分分流,从而相对于击穿电压降低钳位电压。 TVS装置被封装成具有四个焊料凸块(211-214)的倒装芯片(202)。 提交摘要的理解是,根据37 C.F.R.不会将其用于解释或限制索赔的范围或含义。 §1.72(b)。
    • 3. 发明授权
    • Receptacle assembly with both insulation displacement connector bussing
and friction connector coupling of power conductors to surge suppressor
circuit
    • 插座组件与绝缘位移连接器总线和摩擦连接器将电源导体耦合到浪涌抑制电路
    • US5251092A
    • 1993-10-05
    • US800629
    • 1991-11-27
    • Peter J. BradyCarol MillerDavid R. Powell
    • Peter J. BradyCarol MillerDavid R. Powell
    • H01R13/506H01R13/66H01R25/00H02H9/04
    • H01R13/6666H01R12/675H01R25/00H01R13/506
    • A power receptacle assembly includes a plurality of AC snap receptacles each having a base containing three insulation displacement connectors and each electrically connected to a female receptacle connector element. A snap-on retainer forces three insulated power conductors into the three insulation displacement connectors causing knife blade edges thereof to displace insulation and electrically connect inner conductor elements of the insulated power conductors. The snap-on retainer of one of the AC snap receptacles also receives three slotted male tab friction fit connectors to electrically connect them to the three power conductors, respectively. The three slotted male tab friction fit connectors are connected to a printed circuit board that interacts with the three power conductors. Each slotted male tab friction fit connector has an elongated slot separating two bifurcated prongs, outer edges of the prongs frictionally engaging inner surfaces of the insulation displacement connectors. Each insulated power conductors extends through one of the elongated slots.
    • 电源插座组件包括多个AC卡扣插座,每个AC卡扣插座具有包含三个绝缘位移连接器并且每个电连接到阴插座连接器元件的底座。 卡扣保持器将三个绝缘的电力导体施加到三个绝缘位移连接器中,使得其刀片边缘位移绝缘并且电连接绝缘电力导体的内部导体元件。 AC卡扣式插座之一的卡扣式保持架还容纳三个开槽的公接头摩擦配合连接器,以将它们分别电连接到三个电源导体。 三个开槽的公接片摩擦配合连接器连接到与三个电源导体相互作用的印刷电路板。 每个开槽的阳片摩擦配合连接器具有分隔两个分叉插脚的细长插槽,插脚的外边缘与绝缘位移连接器的内表面摩擦接合。 每个绝缘电力导体延伸穿过其中一个细长槽。
    • 5. 发明授权
    • Transient voltage suppression device
    • 瞬态电压抑制装置
    • US07361942B1
    • 2008-04-22
    • US11008416
    • 2004-12-09
    • Fred MattesonVenkatesh Panemangalore PaiDonald K. Cartmell
    • Fred MattesonVenkatesh Panemangalore PaiDonald K. Cartmell
    • H01L29/00H01L29/861
    • H01L27/0814H01L27/0817H01L29/861H01L29/866
    • A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage. The TVS device is packaged as a flip chip (202) that has four solder bump pads (211-214). The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
    • 双向瞬态电压抑制(“TVS”)器件(101)包括半导体管芯(201),其具有与阴极 - 阴极连接的第一整流二极管(104)串联的第一雪崩二极管(103) 具有与第二整流二极管(106)串联的第二雪崩二极管(105)的反并联配置也连接阴极至阴极。 TVS器件的所有二极管都在单个半导体衬底(301)上。 芯片具有设置在具有相反导电类型的半导体衬底(301)和具有第一导电类型的高电阻率外延层(305)之间的具有第一导电类型的低电阻率掩埋扩散层(303)。 掩埋扩散层将大部分瞬态电流从第一雪崩二极管和第一整流二极管之间的外延层的一部分分流,从而相对于击穿电压降低钳位电压。 TVS装置被封装成具有四个焊料凸块(211-214)的倒装芯片(202)。 提交摘要的理解是,根据37 C.F.R.不会将其用于解释或限制权利要求的范围或含义。 §1.72(b)。