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1. 发明授权

US5513330A Apparatus for superscalar instruction predecoding using cached instruction lengths 失效
标题翻译：超标量指令装置，使用缓存指令长度进行预编码
公开(公告)号：US5513330A
公开(公告)日：1996-04-30
申请号：US143549
申请日：1993-10-27
申请人： David R. Stiles
发明人： David R. Stiles
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3804 , G06F9/30149 , G06F9/3816 , G06F9/3822
摘要： A method and apparatus for eliminating the delay in a parallel processing pipeline. In a parallel processing pipeline system, a circuitry is provided to determine the length and align two instructions in parallel. Parallel decoding circuitry is provided for decoding and executing the two instructions. A branch prediction cache stores the target instruction and next sequential instruction, and is tagged by the address of the branch instruction, as in the prior art. In addition, however, the branch prediction cache also stores the length of the first and second instructions and the address of the second instruction. This additional data allows the target and next sequential instructions to be directly aligned and presented to the parallel decoding circuits without waiting for a calculation of their lengths and starting addresses.
摘要翻译：一种用于消除并行处理流水线中的延迟的方法和装置。在并行处理流水线系统中，提供电路以确定长度并并行地对准两条指令。提供并行解码电路用于解码和执行两个指令。分支预测高速缓存存储目标指令和下一个顺序指令，并且如现有技术那样被分支指令的地址标记。然而，此外，分支预测高速缓存还存储第一和第二指令的长度以及第二指令的地址。该附加数据允许目标和下一个顺序指令直接对齐并呈现给并行解码电路，而不用等待其长度和起始地址的计算。

2. 发明授权

US5394351A Optimized binary adder and comparator having an implicit constant for an input 失效
标题翻译：优化的二进制加法器和比较器具有输入的隐式常数
公开(公告)号：US5394351A
公开(公告)日：1995-02-28
申请号：US212516
申请日：1994-03-11
申请人： Larry Widigen , Elliot A. Sowadsky
发明人： Larry Widigen , Elliot A. Sowadsky
IPC分类号： G06F7/02 , G06F7/50 , G06F7/505
CPC分类号： G06F7/505 , G06F7/026
摘要： A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation circuitry. The special CSA uses two different bit cells depending upon whether that bit position in the constant input is a one or a zero. The three-input comparator can be modified to be a three-input adder by using a full carry-propagate adder (CPA). By taking into account a priori restrictions on the possible input operands, these arithmetic circuits are smaller and more efficient than conventional adders and comparators, which must be designed to deal with all possible input operands.
摘要翻译：一个三输入比较器，其中一个输入是一个隐式常数，由特殊的进位保存加法器（CSA）形成，随后是进位传播电路。特殊CSA使用两个不同的位单元，取决于常数输入中的位位置是一位还是零位。通过使用全进位传播加法器（CPA），三输入比较器可以修改为三输入加法器。通过考虑对可能的输入操作数的先验限制，这些运算电路比传统的加法器和比较器更小且更有效，这些加法器和比较器必须被设计为处理所有可能的输入操作数。

3. 发明授权

US5517440A Optimized binary adders and comparators for inputs having different widths 失效
公开(公告)号：US5517440A
公开(公告)日：1996-05-14
申请号：US434162
申请日：1995-05-02
申请人： Larry Widigen , Elliot A. Sowadsky
发明人： Larry Widigen , Elliot A. Sowadsky
IPC分类号： G06F7/02 , G06F7/50 , G06F7/509 , G06F9/302 , G06F9/38 , G06F7/38
CPC分类号： G06F7/509 , G06F7/026 , G06F7/505 , G06F9/3001 , G06F9/3802 , G06F9/3842 , G06F2207/3816
摘要： A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a similar way: the low-order bits are computed with a conventional carry save adder (CSA) followed by a carry propagate adder (CPA), while the high-order bits are computed with an incrementer and selection logic. The first and second circuits are combined to form a third arithmetic circuit that takes four input operands, the first of which is wider than the other three, and speculatively computes two results: (1) the sum of the first and second input operands; and (2) the sum of the first, third, and fourth input operands. This combined circuit contains all of the elements of the first two circuits, but shares a single incrementer. A degenerate case of the third circuit occurs when the second and third inputs are common. This degenerate case has particular application to superscalar instruction pointer updates for variable length instructions. By taking into account a priori restrictions on the possible input operands, these circuits are smaller and more efficient than conventional adders and comparators, which must be designed to deal with all possible input operands.

4. 发明授权

US5511175A Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency 失效
标题翻译：方法一种用于存储到指令流检测和维持分支预测高速缓存一致性的装置
公开(公告)号：US5511175A
公开(公告)日：1996-04-23
申请号：US326409
申请日：1994-10-20
申请人： John G. Favor , Korbin Van Dyke , David R. Stiles
发明人： John G. Favor , Korbin Van Dyke , David R. Stiles
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3812 , G06F9/3804 , G06F9/3844 , G06F9/3863
摘要： The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache. Upon such a detection, that entry in the instruction cache is invalidated, and the corresponding entry in the branch prediction cache is invalidated. A subsequent attempt to use an instruction in the branch prediction cache which has been invalidated will detect that it is not valid, and will instead go to main memory to fetch the instruction, where it has been modified.
摘要翻译：本发明提供了当执行的指令尝试改变这样的指令（“存储到指令流”）时更新分支预测高速缓存中的两个指令和最近提供给来自高速缓存的指令流水线的指令。分支预测高速缓存（BPC）包括识别导致分支的指令的地址的标签，在每个分支指令的最后出现时被分支的目标地址的记录以及从该目标开始的前几个指令的副本地址。提供单独的指令高速缓存用于指令的正常执行，并且从系统总线写入分支预测高速缓存的所有指令也必须存储在指令高速缓存中。指令高速缓存监视系统总线以尝试写入指令高速缓存中包含的指令的地址。在这种检测中，指令高速缓存中的该条目无效，并且分支预测高速缓存中的相应条目无效。随后尝试使用已经无效的分支预测高速缓存中的指令将检测到它无效，并且将转到主存储器以获取已经被修改的指令。

5. 发明授权

US5454117A Configurable branch prediction for a processor performing speculative execution 失效
公开(公告)号：US5454117A
公开(公告)日：1995-09-26
申请号：US112572
申请日：1993-08-25
申请人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein B. Smith, III
发明人： David L. Puziol , Korbin S. Van Dyke , Larry Widigen , Len Shar , Walstein B. Smith, III
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3806 , G06F9/3848
摘要： In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding. In a third aspect of the invention, Hit/Miss information from a Branch Prediction Cache (BPC) can optionally be used in formulating the next state value of an addressed two-bit counter stored in a correlation-based branch history table. Since a Miss in the BPC may indicate that this branch has not been encountered recently, whatever state currently exists can be optionally forced to a state that is based solely on whether the branch is resolved taken or not. This feature may be enabled and disabled under software control. In a fourth aspect of the invention, information from the instruction decoder is optionally used to override the correlation-based branch history table based prediction for select branch instructions. This feature may be enabled and disabled under software or hardware control.

6. 发明授权

US5442757A Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts 失效
标题翻译：具有分布式管道控制的计算机处理器，允许功能单元在保持精确中断的同时完成操作
公开(公告)号：US5442757A
公开(公告)日：1995-08-15
申请号：US25439
申请日：1993-03-03
申请人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John G. Favor , Dale R. Greenley , Robert A. Cargnoni
发明人： Harold L. McFarland , David R. Stiles , Korbin S. Van Dyke , Shrenik Mehta , John G. Favor , Dale R. Greenley , Robert A. Cargnoni
IPC分类号： G06F9/30 , G06F9/308 , G06F9/318 , G06F9/34 , G06F9/355 , G06F9/38 , G06F11/36 , G06F15/78 , G06F15/16
CPC分类号： G06F11/3648 , G06F15/8053 , G06F9/30003 , G06F9/30018 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30189 , G06F9/34 , G06F9/3555 , G06F9/38 , G06F9/3804 , G06F9/3812 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F9/3885
摘要： A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.
摘要翻译：流水线控制系统分布在处理器（10）中的功能单元（15,17,20,25）上。解码器逻辑（12）向功能单元发出每个具有关联标签的操作，最多允许n个操作被显示。单元执行操作并将终止信息报告回解码器逻辑，但不能不可逆转地改变机器的状态。基于终止信息，解码器逻辑依次退出正常终止的操作。如果操作异常终止，则解码器逻辑指示单元退出包括并晚于异常终止的操作的那些操作。

7. 发明授权

US5414820A Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture 失效
标题翻译：交叉传输，以最大化双总线架构中的有效带宽
公开(公告)号：US5414820A
公开(公告)日：1995-05-09
申请号：US215232
申请日：1994-03-21
申请人： Harold L. McFarland , Allen P. Ho
发明人： Harold L. McFarland , Allen P. Ho
IPC分类号： G06F13/364 , G06F13/40 , G06F13/36
CPC分类号： G06F13/364 , G06F13/4031
摘要： A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as a master for both the NexBus and the AB. While it would be possible to have the adapter always request the AB (which also requires the NexBus), that would slow down NexBus operations to the bandwidth of the AB. This problem is avoided by providing two request lines for each adapter, -NREQ (NexBus only) and -AREQ (both buses), having the adapter normally assert -NREQ first. However, if the addressed device is on the AB, the ABI automatically detects this fact and attempts to do a crossing transfer to the AB, even though the request was for the NexBus only. If the ABI is unable to do the crossing transfer because the AB was busy, the ABI automatically causes the NexBus adapter to retry the request using the -AREQ line. Thus the slower AB is only accessed when actually necessary.
摘要翻译：一种双总线架构，包括称为NexBus（20）的高速系统总线，以及称为备用总线或AB（25）的较慢外设总线。 NexBus和AB由包括仲裁器（50）和备用总线接口（ABI）（60）的控制逻辑（45）耦合。 ABI被视为NexBus和AB的主控。虽然可以让适配器总是请求AB（也需要NexBus），但这会使NexBus的运行速度降低到AB的带宽。通过为每个适配器-NREQ（仅限NexBus）和-AREQ（两个总线）提供两条请求线，使适配器通常首先将-NREQ置为-NREQ来避免此问题。然而，如果寻址的设备在AB上，则ABI会自动检测到此事实，并尝试对AB进行交叉转移，即使该请求仅适用于NexBus。如果由于AB忙，ABI无法进行交叉转移，ABI会自动使NexBus适配器使用-AREQ线重试该请求。因此，只有在实际需要时才能访问较慢的AB。

8. 发明授权

US5572159A Voltage-controlled delay element with programmable delay 失效
标题翻译：具有可编程延迟的电压控制延迟元件
公开(公告)号：US5572159A
公开(公告)日：1996-11-05
申请号：US339328
申请日：1994-11-14
申请人： Harold L. McFarland
发明人： Harold L. McFarland
IPC分类号： G05F1/46 , G05F3/26 , H03K5/00 , H03K5/13 , H03K17/28
CPC分类号： G05F3/262 , G05F1/466 , H03K5/131 , H03K5/133 , H03K2005/00202
摘要： A voltage-controlled delay element utilizes a current-starved inverter configuration with a feedback path that ensures a rapid discharge of the storage node to ground once the desired delay time has elapsed. The circuit comprises a circuit path for charging the storage node (preferably rapidly), a first pull-down path capable of discharging the storage node at a rate determined by the control voltage, a second pull-down path capable of rapidly discharging the storage node, an output inverter, and a feedback connection between the output terminal of the output inverter and the second pull-down path to rapidly discharge the storage node when the output voltage starts rising. The circuit further comprises a means for programmably adjusting the delay in response to logic signals.
摘要翻译：电压控制延迟元件利用具有反馈路径的电流饥饿逆变器配置，其确保一旦所需的延迟时间过去，存储节点快速放电到地面。电路包括用于对存储节点（优选地快速）充电的电路，能够以由控制电压确定的速率对存储节点进行放电的第一下拉路径，能够快速地将存储节点放电的第二下拉路径输出反相器和输出反相器的输出端子与第二下拉路径之间的反馈连接，以便在输出电压开始上升时快速放电存储节点。电路还包括用于响应于逻辑信号可编程地调整延迟的装置。

9. 发明授权

US5515518A Two-level branch prediction cache 失效
标题翻译：两级分支预测缓存
公开(公告)号：US5515518A
公开(公告)日：1996-05-07
申请号：US270855
申请日：1994-07-05
申请人： David R. Stiles , John G. Favor , Korbin S. Van Dyke
发明人： David R. Stiles , John G. Favor , Korbin S. Van Dyke
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/3804 , G06F9/3848
摘要： AN improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.
摘要翻译： AN改进的使用混合高速缓存结构的分支预测高速缓存（BPC）方案。 BPC提供两级分支信息缓存。完全关联的第一级BPC是浅而宽的结构（36个32字节的条目），其缓存有限数量的分支指令的全部预测信息。第二个直接映射级别BPC是一个深而窄的结构（256个2字节条目），它仅缓存部分预测信息，但对于大量的分支指令则是这样做的。当每个分支指令被取出和解码时，其地址用于在两个分支预测高速缓存中执行并行查找。

10. 发明授权

US5418736A Optimized binary adders and comparators for inputs having different widths 失效
标题翻译：对于具有不同宽度的输入，优化的二进制加法器和比较器
公开(公告)号：US5418736A
公开(公告)日：1995-05-23
申请号：US212514
申请日：1994-03-11
申请人： Larry Widigen , Elliot A. Sowadsky
发明人： Larry Widigen , Elliot A. Sowadsky
IPC分类号： G06F7/02 , G06F7/50 , G06F7/509 , G06F9/302 , G06F9/38 , G06F7/38
CPC分类号： G06F7/509 , G06F7/026 , G06F7/505 , G06F9/3001 , G06F9/3802 , G06F9/3842 , G06F2207/3816
摘要： A first two-input adder computes the sum of one wider and one narrower input by combining a conventional adder for the low-order bits with an incrementer and selection logic for the high-order bits. A second three-input adder computes the sum of one wider and two narrower inputs in a similar way: the low-order bits are computed with a conventional carry save adder (CSA) followed by a carry propagate adder (CPA), while the high-order bits are computed with an incrementer and selection logic. The first and second circuits are combined to form a third arithmetic circuit that takes four input operands, the first of which is wider than the other three, and speculatively computes two results: (1) the sum of the first and second input operands; and (2) the sum of the first, third, and fourth input operands. This combined circuit contains all of the elements of the first two circuits, but shares a single incrementer. A degenerate case of the third circuit occurs when the second and third inputs are common. This degenerate case has particular application to superscalar instruction pointer updates for variable length instructions. By taking into account a priori restrictions on the possible input operands, these circuits are smaller and more efficient than conventional adders and comparators, which must be designed to deal with all possible input operands.
摘要翻译：第一双输入加法器通过组合用于低阶比特的常规加法器与递增器和高位比特的选择逻辑组合来计算一个较宽和一个较窄输入的和。第二个三输入加法器以类似的方式计算一个较宽和两个较窄输入的和：低位是用常规进位保存加法器（CSA）跟随进位传播加法器（CPA）计算的，而高位使用递增器和选择逻辑计算顺序位。组合第一和第二电路以形成第三运算电路，该运算电路采用四个输入操作数，第一运算电路的第一运算电路比第三运算电路的第一运算电路的运算电路的宽度大，而推测性地计算出两个结果：（1）第一和第二输入操作数之和; 和（2）第一，第三和第四输入操作数之和。该组合电路包含前两个电路的所有元件，但共享单个增量器。当第二和第三输入是共同的时，发生第三电路的退化情况。这种退化情况特别适用于可变长度指令的超标量指令指针更新。通过考虑对可能的输入操作数的先验限制，这些电路比传统的加法器和比较器更小且更有效，这些加法器和比较器必须被设计为处理所有可能的输入操作数。

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