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2. 外观设计

USD421003S Analog cellular telephone 失效
公开(公告)号：USD421003S
公开(公告)日：2000-02-22
申请号：US98040
申请日：1998-12-21
申请人： Shannon R. Bynum , Daniel C. J. LaMendola , Ida A. Gutierrez , Michael C. Wuensch , Etsuro Kawasako
设计人： Shannon R. Bynum , Daniel C. J. LaMendola , Ida A. Gutierrez , Michael C. Wuensch , Etsuro Kawasako

3. 发明授权

US5878039A Bus rate adaptation and time slot assignment circuit for a sonet multiplex system 失效
标题翻译：用于Sonet多路复用系统的总线速率适配和时隙分配电路
公开(公告)号：US5878039A
公开(公告)日：1999-03-02
申请号：US637413
申请日：1996-04-24
申请人： Steven S. Gorshe , Robert W. Brooks, Jr.
发明人： Steven S. Gorshe , Robert W. Brooks, Jr.
IPC分类号： H04J3/16 , H04Q11/04 , H04J3/22
CPC分类号： H04J3/1611 , H04Q11/0478 , H04J2203/0089 , H04Q2213/1301 , H04Q2213/13204 , H04Q2213/1329 , H04Q2213/13297 , H04Q2213/13332 , H04Q2213/13393 , H04Q2213/13399
摘要： An interface device is provided which may be used to perform rate adaptation and time slot assignment, in either the transmit or receive directions, in a multiplexing unit for interfacing a high rate optical carrier line to a plurality of lower rate information carrier lines. The high rate optical carrier line may be a SONET or SDH carrier line. The interface device according to the present invention may be operationally configured to provide data rate adaptation and time slot assignment between an optical carrier line operating at an OC-12 rate with lower rate lines operating according to OC-3, OC-1, DS-3, or DS-1 protocols, or even virtual channels. A plurality of identical interface devices may be cascaded together and used to perform interface support for various channels operating at various rates, merely by manipulating the operational configuration of the individual interface devices in the cascade.
摘要翻译：提供一种接口装置，其可以用于在用于将高速率光载波线路连接到多个较低速率信息载体线路的多路复用单元中的发射或接收方向中执行速率适配和时隙分配。高速光载波线路可以是SONET或SDH载波线路。根据本发明的接口设备可以可操作地被配置为在以OC-12速率工作的光载波线路与根据OC-3，OC-1，DS-1，...之间运行的较低速率线路之间提供数据速率适配和时隙分配， 3或DS-1协议，甚至虚拟通道。多个相同的接口设备可以级联在一起，并且用于仅通过操纵级联中的各个接口设备的操作配置来对以各种速率操作的各种通道执行接口支持。

4. 发明授权

US5848065A Optimized universal card slot system for sonet multiplex equipment 失效
标题翻译：优化通用卡槽系统，用于sonet复用设备
公开(公告)号：US5848065A
公开(公告)日：1998-12-08
申请号：US584193
申请日：1996-01-11
申请人： Steven S. Gorshe , Robert W. Brooks, Jr.
发明人： Steven S. Gorshe , Robert W. Brooks, Jr.
IPC分类号： H04J3/06 , H04J3/16 , H04Q11/04 , H05K7/14 , H04J3/02
CPC分类号： H04Q11/0421 , H04J3/1611 , H05K7/1424 , H04J2203/0026 , H04J3/0685
摘要： A universal tributary interface group approach for SONET multiplex equipment in which the shelf is partitioned into regions and each region can be provisioned to support different service types. The universal tributary group system includes an equipment shelf having a backplane. The equipment shelf is partitioned into regions called tributary groups which are each capable of accepting tributary units having compatible bus widths and clock rates. Removable card guides may be inserted into the tributary group spaces so that tributary interface units of different heights and widths may be placed in the tributary group spaces. Additionally, a plurality of bus segments run along the backplane to electrically connect a time slot interchange unit to card slots in the tributary groups. Each of the bus segments is capable of being provisioned to use a bus rate compatible with the data requirements of the tributary group it services.
摘要翻译：一种用于SONET多路复用设备的通用支路接口组方法，其中可以将架子划分为区域，并且每个区域可以被提供以支持不同的服务类型。通用支流组系统包括具有背板的设备架。设备架被划分为称为支流组的区域，每个区域能够接收具有兼容的总线宽度和时钟速率的支路单元。可拆卸的卡片指南可以插入到支流组空间中，使得不同高度和宽度的支流接口单元可以放置在支流组空间中。此外，多个总线段沿着背板延伸，以将时隙交换单元电连接到支路组中的卡槽。每个总线段都能够被配置为使用与其服务的支路组的数据要求兼容的总线速率。

5. 发明授权

US5815490A SDH ring high order path management 失效
标题翻译： SDH环高阶路径管理
公开(公告)号：US5815490A
公开(公告)日：1998-09-29
申请号：US559884
申请日：1995-11-20
申请人： Tsu-kai Lu
发明人： Tsu-kai Lu
IPC分类号： H04J3/08 , H04Q11/04 , H04L12/24
CPC分类号： H04J3/085 , H04J2203/0058 , H04J2203/006
摘要： A method of managing a telecommunication subnetwork system composed of a number of network elements coupled together through an optical medium to form a Synchronous Digital Hierarchy (SDH) network ring. Each of the network elements receives upon initiation or reconfiguration and then stores an identical ring table or knowledge database that is composed of data in a predetermined format and structure. The ring table defines the ring type and ring identification, number of nodes, ring status, node identification, sequence, and status, and provides ring provisioning tables and embedded SDH ring path identification/status information. The ring table is utilized in each of the network elements for provisioning and other management type functions common within a SDH ring environment.
摘要翻译：一种管理由通过光学介质耦合在一起以形成同步数字体系（SDH）网络环的多个网络元件组成的电信子网系统的方法。每个网络元件在启动或重新配置时接收，然后存储由预定格式和结构的数据组成的相同的环表或知识数据库。环表定义环类型和环标识，节点数，环状态，节点标识，序列和状态，并提供环配置表和嵌入式SDH环路标识/状态信息。在每个网络元件中使用环表用于供应和SDH环环境中通用的其他管理类型功能。

6. 发明授权

US5367598A Interface chassis for fiber optic transport system 失效
标题翻译：光纤传输系统的接口机箱
公开(公告)号：US5367598A
公开(公告)日：1994-11-22
申请号：US140784
申请日：1993-10-21
申请人： William R. Devenish, III , Gustav J. Vercruyssen , Antonius B. Dirriwachter
发明人： William R. Devenish, III , Gustav J. Vercruyssen , Antonius B. Dirriwachter
IPC分类号： H04B10/00 , G02B6/44 , H04Q1/04 , G02B6/36
CPC分类号： G02B6/4454 , G02B6/4452 , G02B6/4455
摘要： An interface housing which has a fiber spool to store slack in the fiber trunks and a card cage to interface the trunk mounted on the door of the housing. The door is hinged on one side of the housing so that, when the door swings open, the entire card cage and fiber spool are clear of the housing and readily accessible and releases the PCB lock. A ribbon connector connects the back plane of the card cage to an interface terminal board on the wall of the housing to which external wire-wrap and/or RJ48X connections may be made. Backup batteries in a tray are disposed along the bottom of the housing and secured in place with a cover. When the housing door swings shut, the fiber optic spool fits in front of back-up batteries in the tray and the card cage fits over the batteries.
摘要翻译：一个接口壳体，其具有用于在纤维树干中存储松弛的光纤卷轴和用于与安装在壳体的门上的干线相接合的卡笼。门铰接在外壳的一侧，使得当门摆动打开时，整个卡笼和光纤线轴都没有外壳，容易接近并释放PCB锁。带状连接器将卡笼的背面连接到外壳的壁上的接口端子板，可以制成外部线缠绕和/或RJ48X连接。托盘中的备用电池沿着壳体的底部设置并用盖子固定就位。当外壳门摆动关闭时，光纤卷轴安装在托盘中的备用电池的前面，卡笼安装在电池上。

7. 发明授权

US5337208A In-line AC current limiter 失效
标题翻译：在线交流限流器
公开(公告)号：US5337208A
公开(公告)日：1994-08-09
申请号：US808875
申请日：1991-12-18
申请人： Steven E. Hossner
发明人： Steven E. Hossner
IPC分类号： H02H9/02 , H02H3/24
CPC分类号： H02H9/02
摘要： An AC current limiter, which is connected in series with a transmission line and which operates in two modes, a conductive mode and a protective mode, includes first and second transistors coupled in parallel with first and second diodes, respectively and the emitters of the first and second transistors serially coupled by a sensing element. First and second gain control networks are couple to the first and second transistors, respectively, to permit control of the gain in the first and second transistors. More particularly, as line current increases to a limiting value, the circuit operates in the protective mode. The voltage across the sensing causes a transistor in one of the first and second networks to turn on, thus diverting current from the respective first and second transistors connected in series with the transmission line. Therefore, line current is limited to a predetermined value. When the current through the circuit reverses, the other transistor and respective gain control network limits current flowing in the opposite direction.
摘要翻译：与传输线串联连接并以两种模式工作的导电模式和保护模式的AC限流器分别包括与第一和第二二极管并联耦合的第一和第二晶体管，第一和第二二极管的发射极以及由感测元件串联耦合的第二晶体管。第一和第二增益控制网络分别耦合到第一和第二晶体管，以允许控制第一和第二晶体管中的增益。更具体地，当线电流增加到极限值时，电路工作在保护模式。感测两端的电压使得第一和第二网络中的一个中的晶体管导通，从而使来自与传输线串联连接的相应第一和第二晶体管的电流转向。因此，线电流被限制为预定值。当通过电路的电流反向时，另一个晶体管和相应的增益控制网络限制电流沿相反方向流动。

8. 外观设计

USD325909S Combined mobile cellular telephone handset and transporter 失效
公开(公告)号：USD325909S
公开(公告)日：1992-05-05
申请号：US710898
申请日：1991-05-31
申请人： David A. Shambley , Tsutomu Okawa , Douglas N. Laube
设计人： David A. Shambley , Tsutomu Okawa , Douglas N. Laube

9. 发明授权

US07124156B2 Apparatus and method for immediate non-sequential state transition in a PN code generator 失效
标题翻译： PN码发生器中立即非顺序状态转换的装置和方法
公开(公告)号：US07124156B2
公开(公告)日：2006-10-17
申请号：US10340001
申请日：2003-01-10
申请人： Gang Yang , Ning Zhang
发明人： Gang Yang , Ning Zhang
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/582 , H04J13/0022 , H04J13/10
摘要： A power of a square matrix is determined in a time approximately proportional to the upper integer of the base-2 logarithm of the order of the matrix. A preferred embodiment uses two types of look-up tables and two multipliers for a matrix of 15×15, and is applied to a pseudorandom noise (PN) sequence phase correlation or state jumping circuit. An exact state of a PN code can be determined or calculated from applying an appropriate offset value into a control circuit. The control circuit can produce a PN sequence state from the offset value and typically does so within one system clock period regardless of the amount of the offset. Once the exact state is determined, it is loaded into a state generator or linear sequence shift register (LSSR) for generating a subsequent stream of bits or symbols of the PN code. The PN generator system may include state computing logic, a maximum length PN generator, a zero insertion circuit and a zero insertion skipping circuit.
摘要翻译：在与矩阵的阶数的基数2对数的上整数大致成比例的时间内确定矩阵的幂。优选实施例对于15×15的矩阵使用两种查找表和两个乘法器，并且被应用于伪随机噪声（PN）序列相位相关或状态跳变电路。可以通过将适当的偏移值应用到控制电路中来确定或计算PN码的精确状态。控制电路可以从偏移值产生PN序列状态，并且通常在一个系统时钟周期内这样做，而与偏移量无关。一旦确定了确切的状态，它被加载到状态发生器或线性序列移位寄存器（LSSR）中，用于产生PN码的后续的比特流或符号。 PN发生器系统可以包括状态计算逻辑，最大长度PN发生器，零插入电路和零插入跳过电路。

10. 外观设计

USD431538S Digital cellular telephone 失效
公开(公告)号：USD431538S
公开(公告)日：2000-10-03
申请号：US98041
申请日：1998-12-21
申请人： Daniel C. J. LaMendola , Troy V. Frandsen , Michael C. Wuensch , Shannon R. Bynum , Etsuro Kawasako
设计人： Daniel C. J. LaMendola , Troy V. Frandsen , Michael C. Wuensch , Shannon R. Bynum , Etsuro Kawasako

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