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1. 发明申请

US20210132146A1 IMAGE TEST SYSTEM AND TEST ASSEMBLY THEREOF 有权
公开(公告)号：US20210132146A1
公开(公告)日：2021-05-06
申请号：US16826334
申请日：2020-03-23
申请人： King Yuan Electronics Co., Ltd.
发明人： Pin-Yan TSAI , Po-Kuan SUNG , Kuang-Che CHENG , Hung-Chan LIN
IPC分类号： G01R31/311 , G01R31/28
摘要： An image test system includes a test assembly and an image capture card. The test assembly is provided for capturing test signals from test objects, and incudes a first transmission interface, a second transmission interface, and an interface conversion circuit. The interface conversion circuit is connected with the first transmission interface, and converts signal transmission forms of the test signals. The second transmission interface is connected with the interface conversion circuit. Besides, the image capture card is provided for connecting with the second transmission interface, and captures image data from the test signals.

2. 发明授权

US10247747B2 Titration module of biochip and tiration test apparatus thereof 有权
公开(公告)号：US10247747B2
公开(公告)日：2019-04-02
申请号：US15424918
申请日：2017-02-06
申请人： King Yuan Electronics Co., Ltd.
发明人： Kuang-Hsiang Liu , Chieh-Wen Lu , His-Hua Chou , Shih-Chan Chine
IPC分类号： G01N35/10 , B01L3/02
摘要： A titration module of biochip includes a base, a plurality of titration units, a plurality of pipelines, a transfer unit, and a control unit. The plural titration units and the plural pipelines are arranged above the base, and that the titration units each is provided, at its lower end, a needle element and a reservoir which are communicated with each other. The transfer unit is arranged on the base, and includes at least one driving device for driving, selectively, the plural titration units and the plural pipelines in a lateral direction (leftward and rightward), a longitudinal direction (frontward and rearward) and a vertical direction (upward and downward), respectively. The control unit is electrically connected with the transfer unit, and controls the same for switching, selectively, the plural titration units and the plural pipelines.

3. 发明申请

US20120041710A1 METHOD AND APPARATUS FOR DETERMINING DISPOSITION OF VIA HOLE ON PRINTED CIRCUIT BOARD 有权
标题翻译：用于确定打印电路板上孔的处理的方法和装置
公开(公告)号：US20120041710A1
公开(公告)日：2012-02-16
申请号：US13233121
申请日：2011-09-15
申请人： Ming-Chin TSAI
发明人： Ming-Chin TSAI
IPC分类号： G06F15/00
CPC分类号： H05K3/0005 , H05K1/0262 , H05K1/115 , H05K2201/093 , H05K2201/09663
摘要： A method for determining disposition of via hole on printed circuit board (PCB), said method comprising the steps of: providing a PCB on which is disposed with a geometric layout and a via hole; providing a line on said PCB for intersecting said geometric layout to form a plurality of points of intersection; defining line segments by segmenting said line at each of said points of intersection to form a plurality of line segments; deleting some of said line segments having one end not being point of intersection for said geometric layout to form a plurality of segmented regions; searching a closed region by repeatedly searching region from any one of the points in said plurality of segmented regions; determining whether a closed region is a smallest closed region; determining whether a via hole is located within said smallest closed region.
摘要翻译：一种用于确定印刷电路板（PCB）上的通孔的配置的方法，所述方法包括以下步骤：提供PCB，其上布置有几何布局和通孔; 在所述PCB上提供一条线，用于与所述几何布局相交以形成多个交点; 通过在每个所述交叉点处分割所述线来形成多个线段来定义线段; 删除一些所述线段，其一端不是所述几何布局的交点，以形成多个分段区域; 通过从所述多个分割区域中的任何一个点反复搜索区域来搜索封闭区域; 确定封闭区域是否是最小的封闭区域; 确定通孔是否位于所述最小封闭区域内。

4. 发明授权

US08085059B2 RF chip test method 有权
标题翻译： RF芯片测试方法
公开(公告)号：US08085059B2
公开(公告)日：2011-12-27
申请号：US12356481
申请日：2009-01-20
申请人： Hsuan-Chung Ko , Hsiu-Ju Chen
发明人： Hsuan-Chung Ko , Hsiu-Ju Chen
IPC分类号： G01R31/00
CPC分类号： G01R31/2822 , G01R27/04 , G01R31/043
摘要： An RF chip test method is disclosed. The RF chip test method includes disposing an RF chip within a chip socket, with the RF chip having at least one RF pin and at least one non-RF pin, the chip socket having conductive elements, and the conductive elements contacting the RF pin and the non-RF pin; connecting the non-RF pin to a ground end and connecting the RF pin to an RF measuring instrument; measuring a S11 parameter of the RF pin using the RF measuring instrument; and comparing the S11 parameter with an allowable range so as to judge the contact condition between the RF pin and the conductive element.
摘要翻译：公开了RF芯片测试方法。 RF芯片测试方法包括将RF芯片设置在芯片插座内，RF芯片具有至少一个RF引脚和至少一个非RF引脚，芯片插座具有导电元件，导电元件接触RF引脚和非RF引脚; 将非RF引脚连接到接地端，并将RF引脚连接到RF测量仪器; 使用RF测量仪器测量RF引脚的S11参数; 并且将S11参数与允许范围进行比较，以便判断RF引脚和导电元件之间的接触状态。

5. 发明授权

US08010468B2 Method for wafer analysis with artificial neural network and system thereof 有权
标题翻译：人工神经网络晶片分析方法及其系统
公开(公告)号：US08010468B2
公开(公告)日：2011-08-30
申请号：US11872414
申请日：2007-10-15
申请人： Ming-Chin Tsai
发明人： Ming-Chin Tsai
IPC分类号： G06E1/00 , G06F15/18
CPC分类号： G06N3/02
摘要： A method for wafer analysis with artificial neural network and the system thereof are disclosed. The method of the system of the present invention has several steps, including: first of all, providing a test unit for wafer test and generating a plurality of test data; next, transmitting the test data to a processing unit for transferring to output data; then, comparing the output data with predictive value and modifying bias and making the output data close to the predictive value, and repeating the steps mentioned above to train this system; finally, analyzing wafers by the trained system. Using this system to analyze wafers not only saves time, but also reduces manpower and the risk resulting from artificial analysis.
摘要翻译：公开了一种使用人造神经网络进行晶片分析的方法及其系统。本发明的系统的方法具有以下几个步骤：首先，提供用于晶片测试的测试单元并产生多个测试数据; 接下来，将测试数据发送到处理单元以传送到输出数据; 然后，将输出数据与预测值进行比较，并修改偏差，使输出数据接近预测值，并重复上述步骤对该系统进行训练; 最后，通过训练有素的系统分析晶片。使用该系统分析晶圆不仅可以节省时间，还可以减少人力和人为分析所产生的风险。

6. 发明授权

US07973548B2 Semiconductor test equipment with concentric pogo towers 有权
标题翻译：半导体测试设备具有同心圆顶塔
公开(公告)号：US07973548B2
公开(公告)日：2011-07-05
申请号：US12591136
申请日：2009-11-10
申请人： Fong Jay Chen
发明人： Fong Jay Chen
IPC分类号： G01R31/02
CPC分类号： G01R31/2889
摘要： A semiconductor test equipment with concentric pogo towers is disclosed, which comprises a base, a tester head, an outer pogo tower, and an inner pogo tower. The inner pogo tower is concentrically received in the outer pogo tower, and a connecting slot of the inner pogo tower is correspondingly engaged with a connecting pin of the outer pogo tower. The outer pogo tower is fixed to the load board together with the inner pogo tower, whereby a plurality of outer pogo pins of the outer pogo tower and a plurality of inner pogo pins of the inner pogo tower are electrically connected to the load board respectively. Therefore, the present invention is capable of expanding the test specifications, but also to change rapidly from different test specifications through replacing a different probe card but without to modify any other hardware.
摘要翻译：公开了一种具有同心圆柱塔的半导体测试设备，其包括基座，测试头，外浮筒塔和内浮筒塔。内部pogo塔同心地收纳在外部的pogo塔内，并且内部的浮标塔的连接槽相应地与外部的浮标塔的连接销接合。外部浮标塔与内部浮标塔一起固定到装载板上，由此分别将外部波哥塔的多个外部弹簧销和内部弹簧塔的多个内部弹簧销电连接到负载板。因此，本发明能够扩展测试规范，而且还可以通过替换不同的探针卡而从不同的测试规范迅速改变，但不改变任何其他硬件。

7. 发明授权

US07847571B2 Semiconductor test system with self-inspection of electrical channel for Pogo tower 有权
公开(公告)号：US07847571B2
公开(公告)日：2010-12-07
申请号：US12458439
申请日：2009-07-13
申请人： Chung Lung Chang
发明人： Chung Lung Chang
IPC分类号： G01R31/02
CPC分类号： G01R35/00 , G01R31/024 , G01R31/2889
摘要： A semiconductor test system with self-inspection of an electrical channel for a Pogo tower is disclosed, which provides a short board and closed loops are formed respectively by providing various kinds of contacts to correspondingly electrically contact various kinds of Pogo pins in the Pogo tower on a load board. A self-inspection controller outputs different inspection signals, through the above-mentioned closed loops, respectively to each power channel, each I/O channel and each drive channel, and a plurality of parameter detection units detect response signals, and the response signals are judged by the self-inspection controller. Based on it, before inspecting a wafer to be tested, the invention is capable of self-inspecting each electrical channel and each Pogo pin on the Pogo tower to see if they are respectively in a normal condition, either in an open or short circuit, or if there exists a leakage condition.

8. 发明授权

US07821277B2 Parallel test fixture for mixed signal integrated circuits 有权
标题翻译：混合信号集成电路并联测试夹具
公开(公告)号：US07821277B2
公开(公告)日：2010-10-26
申请号：US12144529
申请日：2008-06-23
申请人： Cheng-Chin Ni
发明人： Cheng-Chin Ni
IPC分类号： G01R31/02
CPC分类号： G01R1/07307 , G01R1/06772 , G01R31/3167
摘要： The present invention provides a parallel test fixture for mixed signal integrated circuits (ICs). The fixture includes a multi-layer printed circuit board (PCB). The fixture includes: a test area, which is disposed on a central area of the multi-layer PCB and includes several test regions for a plurality of mixed signal ICs; an analog signal ground layer, which is operationally connected with the analog signals of the mixed signal ICs in the test area; and a digital signal ground layer, which is operationally connected with the digital signals of the mixed signal ICs in the test area. Thereby, when a plurality of mixed signal ICs are parallel tested, not only the problem due to cross-talk could be solved but also the numbers of the layers of the multi-layer PCB could be reduced effectively.
摘要翻译：本发明提供了一种用于混合信号集成电路（IC）的并联测试夹具。该夹具包括多层印刷电路板（PCB）。夹具包括：测试区域，其设置在多层PCB的中心区域上，并且包括用于多个混合信号IC的若干测试区域; 模拟信号接地层，其与测试区域中的混合信号IC的模拟信号可操作地连接; 以及与测试区域中的混合信号IC的数字信号可操作地连接的数字信号接地层。因此，当多个混合信号IC被并联测试时，不仅可以解决串扰问题，而且可以有效地降低多层PCB的层数。

9. 发明申请

US20100211837A1 Semiconductor test system with self-inspection of memory repair analysis 有权
标题翻译：半导体测试系统具有自检内存修复分析
公开(公告)号：US20100211837A1
公开(公告)日：2010-08-19
申请号：US12585016
申请日：2009-09-01
申请人： Chia-Ching Peng
发明人： Chia-Ching Peng
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/44 , G11C29/02 , G11C29/4401
摘要： A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.
摘要翻译：公开了一种具有记忆修复分析自检的半导体测试系统，包括存储器修复分析设备，分析失败存储器和自检控制器。自检控制器控制存储从外部提供的一组模拟故障位地址和一组模拟修复线地址到预先分析故障存储器中，控制存储器修复分析设备执行特定的修复分析操作到一组模拟故障位地址以产生修理线地址信息，并将计算后获得的修复线地址信息与分析失败存储器中的一组模拟维修线地址直接进行比较。因此，在物理进行测试操作之前，如果存储器修复分析装置的异常状况和其中包含的分析失败存储器，本发明能够进行自检。

10. 发明申请

US20100191203A1 System and equipment for persons with stoma 审中-公开
标题翻译：造口人的系统和设备
公开(公告)号：US20100191203A1
公开(公告)日：2010-07-29
申请号：US12460094
申请日：2009-07-10
申请人： Hans H. HARALDSTED
发明人： Hans H. HARALDSTED
IPC分类号： A61F5/448 , A61F5/445
CPC分类号： A61F5/448
摘要： An ostomy appliance for a single ostomy pouch, alternative a couple able pouch, namely an ostomy appliance as a pressure ring; said a flat cylindrical pressure ring, with an outer circularly diameter, and an inner circularly diameter; said which inner circularly diameter in its size is made or chosen so it fit, and touch to the surface of the actually stoma, and where the pressure ring is hold and coupled floating to the system.
摘要翻译：用于单个造口袋的造口术器具，替代一对夫妇袋，即作为压力环的造口术器具; 所述平坦的圆柱形压力环具有外部圆形直径和内部圆形直径; 表示其尺寸的内圆直径被制成或选择成使其适合，并且接触实际造口的表面，并且压力环保持并耦合到系统上。

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