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1. 外观设计

USD368097S Modem 失效
公开(公告)号：USD368097S
公开(公告)日：1996-03-19
申请号：US39728
申请日：1995-06-05
申请人： James R. Heberling , Samuel W. Harris
设计人： James R. Heberling , Samuel W. Harris

2. 发明授权

US5179706A Method and apparatus for preventing bus contention problems between two processors 失效
标题翻译：用于防止两个处理器之间的总线争用问题的方法和装置
公开(公告)号：US5179706A
公开(公告)日：1993-01-12
申请号：US428858
申请日：1989-10-30
申请人： Scott C. Swanson , Jeffrey P. Murray
发明人： Scott C. Swanson , Jeffrey P. Murray
IPC分类号： A61F13/15 , G06F13/376
CPC分类号： G06F13/376 , A61F2013/15325 , A61F2013/15967
摘要： A bus access controller. An interface circuit (22) controls the access of a host computer (10) and a microprocessor (23) to one or more UARTs (14, 15). The microprocessor (23), which has no provision for waiting for a data transfer, is required to provide a signal of its intent to perform a data transfer prior to beginning the actual data transfer. The signal is identical to the actual data transfer operation. If the host (10) attempts a data transfer operation while the microprocessor (23) is conducting a data transfer operation, or if the host data transfer cannot be completed prior to the time that the microprocessor data transfer will commence, then the interface circuit (22) signals the host (10) that the data transfer will take additional time by deasserting the I/O READY line (12a). Once the microprocessor data transfer is completed then the I/O READY signal is reasserted and the host data transfer is completed. Bus contention problems and data loss are therefore prevented and the host (10) waiting time is minimized.
摘要翻译：总线访问控制器。接口电路（22）控制主计算机（10）和微处理器（23）到一个或多个UART（14,15）的访问。无需等待数据传输的微处理器（23）需要在开始实际数据传输之前提供其意图进行数据传输的信号。该信号与实际数据传输操作相同。如果主机（10）在微处理器（23）进行数据传送操作时尝试进行数据传送操作，或者在微处理器数据传输开始之前无法完成主机数据传送，则接口电路 22）通过解除I / O READY线（12a）来通知主机（10）数据传输将需要额外的时间。一旦微处理器数据传输完成，则I / O READY信号被重新发送，主机数据传输完成。因此防止总线争用问题和数据丢失，并且主机（10）的等待时间被最小化。

3. 发明授权

US5179661A Method and apparatus for serial data flow control 失效
标题翻译：串行数据流控制的方法和装置
公开(公告)号：US5179661A
公开(公告)日：1993-01-12
申请号：US429065
申请日：1989-10-30
申请人： John A. Copeland, III , John W. Jerrim , Scott C. Swanson
发明人： John A. Copeland, III , John W. Jerrim , Scott C. Swanson
IPC分类号： H04L12/56 , H04L29/06
CPC分类号： H04L47/10 , H04L29/06
摘要： A data flow controller (150) for monitoring and automatically controlling the flow of serial data from a remote transmitter to a host device. A serial communications card (11) provides an interface between a remote transmitter connected to a serial port connector (20) and a host device (10). The card (11) contains a UART (14) which has a buffer. A counter (151) counts the number of bytes received by the UART (14) since the last time that the host (10) read all the data in the buffer. If the number exceeds a predetermined portion of the buffer capacity the counter output (Q11) will go high, thereby disabling the counter and sending a control signal (DTR, RTS) to the remote transmitter to stop sending data. Once the host (10) has read all the data in the buffer the UART (14) provides a signal (-RXREADY) which resets the counter (151), thereby causing the output (Q11) to go low, thereby allowing the remote transmitter to resume sending data. The counter (151) is held in a reset state until the buffer has received at least one byte of data. Data flow control is therefore obtained without the intervention of the host (10).

4. 发明授权

US5070514A Method and apparatus for clearing data path in half duplex modem receiver while maintaining dynamic parameters 失效
标题翻译：在保持动态参数的同时，在半双工调制解调器接收机中清除数据路径的方法和装置
公开(公告)号：US5070514A
公开(公告)日：1991-12-03
申请号：US454180
申请日：1989-12-21
申请人： Taruna Tjahjadi
发明人： Taruna Tjahjadi
IPC分类号： H04L5/16 , H04M11/06
CPC分类号： H04M11/06 , H04L5/16
摘要： A DSP receiver for a fast turnaround modem, particularly suited for a half duplex fast turnaround modem which prevents destruction of communication channel related adaptive equalizer parameters upon loss of carrier. Upon detection of carrier loss, after sufficient time has been allowed for the last informational data bits to pass through the receiver's adaptive equalizer, the output of the equalizer's FIR filter delay line is looped back, via a multiplexer, to the input of the equalizer so that communications channel related samples are continuously provided to the equalizer to maintain the parameters at values based on the receiver's actual experience with data transmitted through the communications channel to which it is connected. A delay timer responsive to the loss of carrier signal will terminate updating of the adaptive equalizer parameters a predetermined time after loss of carrier. Alternately, detection of a standard end of data flag in the data stream will also terminate parameter update.
摘要翻译：用于快速周转调制解调器的DSP接收器，特别适用于半双工快速周转调制解调器，防止在丢失载波时破坏通信信道相关的自适应均衡器参数。在检测到载波丢失时，在允许最后信息数据位通过接收机的自适应均衡器足够的时间之后，均衡器的FIR滤波器延迟线的输出通过多路复用器被环回到均衡器的输入端该通信信道相关样本被连续地提供给均衡器，以便基于接收机的实际体验将参数维持在通过与其连接的通信信道发送的数据的值。响应于载波信号丢失的延迟定时器将在丢失载波之后的预定时间内终止自适应均衡器参数的更新。或者，数据流中标准数据标志结束的检测也将终止参数更新。

5. 外观设计

USD318655S Data communications peripheral 失效
公开(公告)号：USD318655S
公开(公告)日：1991-07-30
申请号：US386492
申请日：1989-07-27
申请人： Frank Bowker , Samuel W. Harris , David Gresham , Mark Hicks
设计人： Frank Bowker , Samuel W. Harris , David Gresham , Mark Hicks

6. 发明授权

US4972436A High performance sigma delta based analog modem front end 失效
标题翻译：高性能Σ-Δ模拟调制解调器前端
公开(公告)号：US4972436A
公开(公告)日：1990-11-20
申请号：US257733
申请日：1988-10-14
申请人： Raouf Y. Halim , Randy D. Nash
发明人： Raouf Y. Halim , Randy D. Nash
IPC分类号： H03M3/02
CPC分类号： H03M3/348 , H03M3/458
摘要： An improved analog front end circuit for a high performance modem comprising an oversampling sigma delta modulator analog-to-digital converter which employs a novel four phase clocked MOSFET switched capacitor integrator. The integrator is switched in a manner as to eliminate signal dependent charges in the MOSFET switches. The sigma delta modulator shifts quantization noise of the analog-to-digital conversion process out of baseband of the analog signal. A novel integrated decimating FIR low pass filter filters the quantization noise from the digital output signals, and reduces the number of digital signals to obtain a sufficient number of signal samples in order to provide operation at high speeds, for example 9600 bps. The improved four phase switched capacitor integrator is also suitable for use in sigma delta modulator circuits, analog-to-digital converter circuits, integrating cirucits, and the like. A novel return-to-zero circuit eliminates distortion in a sigma delta modulator based analog-to-digital conversion process which can result from unequal rise and fall times of the digital output, by insuring that the energies in signals represented by a "one" and signals represented by a "zero" are equal, even during portions of the bit stream wherein there is a consecutive sequence of "ones".
摘要翻译：用于高性能调制解调器的改进的模拟前端电路包括采用新型四相时钟MOSFET开关电容器积分器的过采样Σ-Δ调制器模数转换器。积分器的切换方式是消除MOSFET开关中的信号相关电荷。 Σ-Δ调制器将模拟 - 数字转换处理的量化噪声移出模拟信号的基带。一种新颖的集成抽取FIR低通滤波器从数字输出信号中滤除量化噪声，并且减少数字信号的数量以获得足够数量的信号样本，以提供高速操作，例如9600bps。改进的四相开关电容器积分器也适用于Σ-Δ调制器电路，模数转换器电路，集成电路等。一种新颖的归零电路消除了由于数字输出的不等上升和下降时间引起的基于Σ-Δ调制器的模数转换过程中的失真，通过确保由“一”表示的信号中的能量，并且即使在存在连续序列“1”的比特流的部分期间，由“零”表示的信号也相等。

7. 发明授权

US4849703A Method and apparatus for generating a data sampling clock locked to a baud clock contained in a data signal 失效
标题翻译：用于产生锁定在包含在数据信号中的波特率时钟的数据采样时钟的方法和装置
公开(公告)号：US4849703A
公开(公告)日：1989-07-18
申请号：US176692
申请日：1988-04-01
申请人： Matthew F. Easley , German E. Correa , Randy D. Nash , Cynthia A. Panella , Taruna Tjahjadi
发明人： Matthew F. Easley , German E. Correa , Randy D. Nash , Cynthia A. Panella , Taruna Tjahjadi
IPC分类号： H04J3/06 , H04L7/033 , H04L27/00 , H04L27/08 , H04L27/20 , H04L27/36 , H04L29/06
CPC分类号： H04L7/0334 , H04J3/0605 , H04L27/00 , H04L27/08 , H04L27/2071 , H04L27/362 , H04L29/06 , H04L7/0331
摘要： An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide a recovered baud clock. A detector (233) signals the positive going zero-crossing points of the recovered baud clock. A lead/lag calculator (234) determines which of the signal samples is nearest the zero-crossing point. The calculator (234) then determines whether this and every subsequent 12th sampling point leads or lags the zero-crossing point by inspecting the sign of the recovered baud clock and adjusts the preset inputs of the counter (236) to cause the sample points to occur at the zero-crossing point.
摘要翻译：改进的波特率时钟恢复，调制解调器的同步和数据采样电路。 CODEC（41）以由可预设计数器（236）的采样时钟输出确定的速率对输入信号进行采样。采样信号然后平方（231）并带通滤波（232）以提供恢复的波特率时钟。检测器（233）用信号通知恢复的波特率时钟的正向过零点。引导/延迟计算器（234）确定哪个信号采样最接近过零点。然后，计算器（234）通过检查恢复的波特率时钟的符号来确定该和每个随后的第十二采样点是否引导或滞后过零点，并调整计数器（236）的预设输入以使样本点发生在过零点。

8. 发明授权

US4670887A Multiplexed PSK demodulator 失效
标题翻译：多路复用PSK解调器
公开(公告)号：US4670887A
公开(公告)日：1987-06-02
申请号：US762218
申请日：1985-08-05
申请人： Dale A. Heatherington
发明人： Dale A. Heatherington
IPC分类号： H04L27/227 , H03D3/22 , H04L27/22
CPC分类号： H04L27/2275
摘要： An improved quadrature differential phase shift keyed signal demodulator for use in a modem is shown. A delay circuit (12) delays an input signal for a portion of a baud time. Synchronous detectors (21, 23) mix the original and delayed input signals with coherent reference signals to obtain detected outputs which are alternately provided to a processor (60) by a multiplexer (25). The processor (60) determines the phase shift and provides the demodulated data. An offset baud clock phase locked loop (40) provides a baud clock which is offset by a ninety degree phase lag. The offset baud clock caused the multiplexer (25) to provide detected outputs to the processor (60) for the center one-half of each baud. The result is a demodulator with fewer components and an improved data error rate.
摘要翻译：示出了用于调制解调器的改进的正交差分相移键控信号解调器。延迟电路（12）延迟一部分波特率时间的输入信号。同步检测器（21,23）将原始和延迟的输入信号与相干参考信号混合，以获得由多路复用器（25）交替地提供给处理器（60）的检测输出。处理器（60）确定相移并提供解调数据。偏移波特率时钟锁相环（40）提供波形时钟，偏移90度相位滞后。偏移波特率时钟导致多路复用器（25）向每个波特的中心的一半提供检测到的输出给处理器（60）。结果是具有较少组件和改进的数据错误率的解调器。

9. 发明授权

US4440988A Modem with low part count and improved demodulator 失效
公开(公告)号：US4440988A
公开(公告)日：1984-04-03
申请号：US448980
申请日：1982-12-13
申请人： Dale A. Heatherington
发明人： Dale A. Heatherington
IPC分类号： H04L27/10 , H04L27/30 , H04M11/00
CPC分类号： H04L27/30 , H04L27/10
摘要： An FSK modem for coupling a standard data port (50) to a telephone line (45) in which the signal path between the phone line and the data port passes through a processor (55). The same frequency detection apparatus (83, 192, 180) is used to both demodulate FSK encoded signals and detect the presence of a telephone ringing signal on the line. A pair of impedances (161, 162) provide alternate paths either through an input filtering network (167) or bypassing the network (135, 69) in a manner which allows the ring signals to pass directly to the input (69) of the frequency detector while assuring that only filtered FSK signals reach the input. Also shown is the use of the same frequency synthesizing apparatus (86, 253, 259) for generating FSK output signals and high group DTMF signals with appropriate switchable attenuation (88) provided in this signal path.

10. 发明授权

US5717870A Serial port controller for preventing repetitive interrupt signals 失效
标题翻译：串行端口控制器，用于防止重复的中断信号
公开(公告)号：US5717870A
公开(公告)日：1998-02-10
申请号：US329728
申请日：1994-10-26
申请人： William Gordon Keith Dobson
发明人： William Gordon Keith Dobson
IPC分类号： G06F13/24 , G06F13/38
CPC分类号： G06F13/385 , G06F13/24
摘要： An improved input/output FIFO buffering device with expanded buffers for a universal asynchronous receiver/transmitter (UART) that includes scalable trigger levels for generation of an external service request is disclosed. Standard selectable trigger levels used in a type 16550 UART are provided as well as expanded scalable trigger levels to accommodate the larger buffers. The larger scalable trigger levels may be employed in a manner transparent to an application written for 16 byte buffers so as to physical accommodate higher data rates without requiring applications to know that more buffer space is used. A reinterruptable timer inhibits generation of an interrupt service request until a predetermined period of time after the most recent interrupt request has been serviced. The period of the timer is selectively programmable.
摘要翻译：公开了一种用于通用异步收发器（UART）的扩展缓冲器的改进的输入/输出FIFO缓冲装置，其包括用于产生外部服务请求的可扩展触发电平。提供16550型UART中使用的标准可选触发电平以及扩展的可扩展触发电平，以适应较大的缓冲区。可以以对于16字节缓冲器编写的应用程序透明的方式采用较大的可伸缩触发电平，从而物理上容纳更高的数据速率，而不需要应用程序知道使用更多的缓冲区空间。重新中断定时器禁止生成中断服务请求，直到最近中断请求被服务之后的预定时间段。定时器的周期是有选择的可编程的。

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