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    • 1. 发明授权
    • Intra-pixel frame storage element, array, and electronic shutter method
including speed switch suitable for electronic still camera applications
    • 像素内帧存储元件,阵列和电子快门方法,包括适用于电子静态照相机应用的速度开关
    • US6069376A
    • 2000-05-30
    • US48921
    • 1998-03-26
    • Richard B. Merrill
    • Richard B. Merrill
    • H01L27/146H04N5/353H04N5/374H04N5/3745H01L31/062H01L31/113
    • H04N5/353H01L27/14609H01L27/14623H04N5/37452H04N5/374
    • A storage pixel sensor disposed on a semiconductor substrate comprises a MOS capacitor storage element having a diffusion terminal and a gate terminal. A speed node is connected to the diffusion terminal and biased at either a first control potential or a second control potential, the first potential selected to keep the MOS capacitor in a state of inversion, the second potential selected to keep the MOS capacitor in a state of depletion. A photodiode has an anode connected to a reference potential and a cathode. A semiconductor reset switch has a first terminal connected to the cathode and a second terminal connected to a reset reference potential. A semiconductor transfer switch has a first terminal connected to the cathode and a second terminal connected to the gate terminal of the capacitive storage element. A semiconductor amplifier has an input connected to the gate terminal of the capacitive storage element and an output. The semiconductor reset switch and the semiconductor transfer switch each have a control element connected to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch. A light shield is disposed over a portion of the semiconductor substrate including the second terminal of the semiconductor transfer switch to prevent substantially all photons from entering the portion of the semiconductor substrate. Structures are present for preventing substantially all minority carriers generated in the semiconductor substrate from entering the portion of the semiconductor substrate. A plurality of storage pixel sensors are disposed in an array.
    • 设置在半导体衬底上的存储像素传感器包括具有扩散端子和栅极端子的MOS电容器存储元件。 速度节点连接到扩散端并被偏置在第一控制电位或第二控制电位,所选择的第一电位用于保持MOS电容处于反相状态,所选择的第二电位使MOS电容保持在一个状态 的消耗。 光电二极管具有连接到参考电位的阳极和阴极。 半导体复位开关具有连接到阴极的第一端子和连接到复位参考电位的第二端子。 半导体转移开关具有连接到阴极的第一端子和连接到电容性存储元件的栅极端子的第二端子。 半导体放大器具有连接到电容性存储元件的栅极端子的输入端和输出端。 半导体复位开关和半导体转移开关各自具有连接到用于选择性地激活半导体复位开关和半导体转移开关的控制电路的控制元件。 在包括半导体转移开关的第二端子的半导体衬底的一部分上设置有光屏蔽,以防止基本上所有的光子进入半导体衬底的部分。 存在用于防止在半导体衬底中产生的基本上所有少数载流子进入半导体衬底部分的结构。 多个存储像素传感器被布置成阵列。
    • 6. 发明授权
    • Low leakage active pixel using spacer protective mask compatible with
CMOS process
    • 低泄漏有源像素使用与CMOS工艺兼容的间隔保护掩模
    • US6137127A
    • 2000-10-24
    • US908266
    • 1997-08-07
    • Richard B. Merrill
    • Richard B. Merrill
    • H01L27/146H01L31/0224H01L31/062H01L27/148
    • H01L27/14643H01L27/14609H01L31/022408
    • A pixel cell structure having a nonsilicided photodiode overcomes problems associated with the absorption of incident light by silicided surfaces. Furthermore, a photodiode access transistor having a partially silicided gate is interposed between the photodiode and the pixel cell transistors performing reset and row select functions, thereby allowing isolation of the photodiode from leakage associated with silicided junctions. Selective application of voltage to the transistors of the pixel structure according to a clocking sequence permits interaction of the photodiode and the MOS transistors making up the pixel cell, while minimizing exposure of the photodiode to leakage and stress associated with these silicided MOS transistors.
    • 具有非硅化光电二极管的像素单元结构克服了与硅化物表面吸收入射光有关的问题。 此外,具有部分硅化栅极的光电二极管存取晶体管插入在光电二极管和执行复位和行选择功能的像素单元晶体管之间,从而允许光电二极管与硅化物结的泄漏隔离。 根据时钟顺序对像素结构的晶体管选择性地施加电压允许构成像素单元的光电二极管和MOS晶体管的相互作用,同时最小化光电二极管暴露于​​与这些硅化MOS晶体管相关联的泄漏和应力。