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1. 发明授权

US10013373B1 Multi-level message passing descriptor 有权
公开(公告)号：US10013373B1
公开(公告)日：2018-07-03
申请号：US15344537
申请日：2016-11-06
申请人： BiTMICRO Networks, Inc.
发明人： Ricardo H. Bruce , Bernard Sherwin Leung Chiw , Margaret Anne Nadonga Somera
IPC分类号： G06F13/28 , G06F13/16
CPC分类号： G06F13/28 , G06F13/1673 , G06F2213/2802
摘要： In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.

2. 发明授权

US09916213B1 Bus arbitration with routing and failover mechanism 有权
公开(公告)号：US09916213B1
公开(公告)日：2018-03-13
申请号：US14688209
申请日：2015-04-16
申请人： BiTMICRO Networks, Inc.
发明人： Ricardo H. Bruce , Cyrill Coronel Ponce , Jarmie De La Cruz Espuerta , Marlon Basa Verdan
IPC分类号： G06F13/36 , G06F11/20 , G06F13/40 , G06F13/16
CPC分类号： G06F11/2007 , G06F11/2002 , G06F11/2005 , G06F11/2017 , G06F11/202 , G06F11/2023 , G06F11/2041 , G06F13/1605 , G06F13/366 , G06F13/4031
摘要： In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.

3. 发明授权

US09811461B1 Data storage system 有权
公开(公告)号：US09811461B1
公开(公告)日：2017-11-07
申请号：US14690370
申请日：2015-04-17
申请人： Marvin Dela Cruz Fenol , Jik-Jik Oyong Abad , Precious Nezaiah Umali Pestano
发明人： Marvin Dela Cruz Fenol , Jik-Jik Oyong Abad , Precious Nezaiah Umali Pestano
IPC分类号： G06F12/02 , G06F12/0831
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7203 , G06F2212/7204 , G06F2212/7206 , G06F2212/7207 , G06F2212/7209
摘要： In an embodiment of the invention, a method comprises: requesting an update or modification on a control data in at least one flash block in a storage memory; requesting a cache memory; replicating, from the storage memory to the cache memory, the control data to be updated or to be modified; moving a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update or modification on the control data; and moving the dirty cache link list to a for flush link list and writing an updated control data from the for flush link list to a free flash page in the storage memory.

4. 发明授权

US09720603B1 IOC to IOC distributed caching architecture 有权
公开(公告)号：US09720603B1
公开(公告)日：2017-08-01
申请号：US14216937
申请日：2014-03-17
申请人： Lawrence Moldez Salazar , Bernard Sherwin Leung Chiw
发明人： Lawrence Moldez Salazar , Bernard Sherwin Leung Chiw
IPC分类号： G06F15/167 , G06F3/06
CPC分类号： G06F3/0613 , G06F3/0635 , G06F3/065 , G06F3/067 , G06F12/0804 , G06F12/0813 , G06F12/0868 , G06F2212/1016 , G06F2212/1032 , G06F2212/222 , G06F2212/225 , G06F2212/284
摘要： In an embodiment of the invention, a method which speeds up the transfer of data and increases the data throughput in an IO network comprised of Host Bus Adapters (HBAs)/IO bridges-switches, IO devices, and hosts is described. In the embodiment of the present invention, HBAs and IO bridges-switches utilize a multi-level cache composed of volatile memories (such as SRAM, SDRAM, etc.) and solid-state memories (such as flash, MRAM, etc.). These memories are used to cache the most recently accessed IO data by an active host or by another HBA/IO bridge-switch. Cache content can be from the local IO devices (the ones connected directly to the HBA/IO bridge-switch), from remote IO devices (the ones connected to different HBA/IO bridges/switches), or from both (a portion from local IO devices and another portion from remote IO devices). The combination of these caches from different HBAs/IO bridges-switches creates the cache for all IO devices in the entire network. Multiple copies of the same IO cache are possible depending on the transactions with the hosts.

5. 发明授权

US09501436B1 Multi-level message passing descriptor 有权
标题翻译：多级消息传递描述符
公开(公告)号：US09501436B1
公开(公告)日：2016-11-22
申请号：US14217041
申请日：2014-03-17
申请人： BiTMICRO Networks, Inc.
发明人： Ricardo H. Bruce , Bernard Sherwin Leung Chiw , Margaret Anne Nadonga Somera
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/1673 , G06F2213/2802
摘要： In an embodiment of the invention, a method for to use a two level linked list descriptor mechanism to pass information among flash, memory, and IO controller modules is presented. The method includes creating a first level data structure for one or more first level descriptors; creating a second level data structure for one or more second level descriptors, each second level descriptor having a pointer to tracking information that includes start information, running information, and rewind information for a data DMA; using the one or more second level descriptors, the one or more first level descriptors, and the tracking information for a data DMA; updating the tracking information during the data DMA; and updating the tracking information at the end of the data DMA.
摘要翻译：在本发明的实施例中，提出了一种使用二级链表描述符机制来在闪存，存储器和IO控制器模块之间传递信息的方法。该方法包括为一个或多个第一级描述符创建第一级数据结构; 为一个或多个第二级描述符创建第二级数据结构，每个第二级描述符具有指向跟踪信息的指针，所述跟踪信息包括数据DMA的开始信息，运行信息和倒带信息; 使用一个或多个第二级描述符，一个或多个第一级描述符和数据DMA的跟踪信息; 在数据DMA期间更新跟踪信息; 并在数据DMA结束时更新跟踪信息。

6. 发明授权

US09484103B1 Electronic storage device 有权
标题翻译：电子存储装置
公开(公告)号：US09484103B1
公开(公告)日：2016-11-01
申请号：US14803107
申请日：2015-07-20
申请人： BiTMICRO Networks, Inc.
发明人： Rolando H. Bruce , Reyjan C. Lanuza , Jose Miguel N. Lukban , Mark Ian A. Arcedera , Ryan C. Chong
IPC分类号： G06F12/02 , G11C16/14 , G11C16/26 , G11C16/20 , G11C16/08
CPC分类号： G11C16/14 , G06F3/0679 , G06F12/0246 , G11C16/08 , G11C16/16 , G11C16/20 , G11C16/26
摘要： A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
摘要翻译：公开了一种用于减少使用至少一个擦除限制的存储器件的电子存储设备中的擦除周期的解决方案。

7. 发明授权

US09430386B2 Multi-leveled cache management in a hybrid storage system 有权
标题翻译：混合存储系统中的多级缓存管理
公开(公告)号：US09430386B2
公开(公告)日：2016-08-30
申请号：US14217436
申请日：2014-03-17
申请人： BiTMICRO Networks, Inc.
发明人： Rolando H. Bruce , Elmer Paule Dela Cruz , Mark Ian Alcid Arcedera
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0844 , G06F12/0868 , G06F2212/1016 , G06F2212/217 , G06F2212/225 , G06F2212/313
摘要： A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels.
摘要翻译：描述了具有包括旋转驱动器，闪存装置，SDRAM和SRAM的不同类型的存储装置的混合的混合存储系统。旋转驱动器用作主存储器，提供每单位存储存储器的最低成本。闪存用作旋转驱动器的更高级缓存。提供了用于管理该存储系统的多级缓存的方法，其具有由易失性存储器（SRAM或SDRAM）组成的非常快速的1级缓存以及使用闪存器件阵列的非易失性级别2高速缓存。它描述了一种在旋转驱动器之间分配数据以使缓存更有效率的方法。它还描述了将数据从L1高速缓存和L2高速缓存冲刷到旋转驱动器的有效技术，利用并发闪存设备操作，并发旋转驱动操作和最大化旋转驱动器中的顺序访问类型，而不是相对较慢的随机访问。这里提供的方法可以扩展到具有两个以上缓存级别的系统。

8. 发明授权

US09423457B2 Self-test solution for delay locked loops 有权
标题翻译：用于延迟锁定环路的自检解决方案
公开(公告)号：US09423457B2
公开(公告)日：2016-08-23
申请号：US14214216
申请日：2014-03-14
申请人： Edzel Gerald Dela Cruz Raffiñan
发明人： Edzel Gerald Dela Cruz Raffiñan
IPC分类号： G01R31/02 , G01R25/00 , G01R31/317 , G11C29/02 , G11C29/50
CPC分类号： G01R31/31725 , G01R31/31724 , G11C29/023 , G11C29/028 , G11C29/12 , G11C29/50012
摘要： A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.
摘要翻译：提供内置的自检（BIST）电路和方法来测试第一个和第二个DLL。第一DLL具有第一延迟输入端，第一时钟输入端，用于接收时钟输入信号;以及第一时钟输出端，其提供与时钟输入信号相比延迟的第一时钟输出信号。第二DLL具有第二延迟输入，第二时钟输入被设置为接收时钟输入信号，以及与时钟输入信号相比延迟的第二时钟输出信号。 BIST电路在第一延迟输入端提供第一延迟量，产生第一和第二时钟输出信号之间的起始偏移。如果第一个DLL正常工作，即使在BIST电路为第一和第二延迟输入提供额外的公共延迟量之后，输出信号之间的起始偏移也应保持不变。

9. 发明授权

US09372755B1 Adaptive power cycle sequences for data recovery 有权
标题翻译：用于数据恢复的自适应功率循环序列
公开(公告)号：US09372755B1
公开(公告)日：2016-06-21
申请号：US13253912
申请日：2011-10-05
申请人： Rolando H. Bruce , Leonila T. Bruce , Richard A. Cantong , Marizonne O. Fuentes
发明人： Rolando H. Bruce , Richard A. Cantong , Marizonne O. Fuentes
IPC分类号： G06F11/00 , G06F11/14 , G06F3/06
CPC分类号： G06F11/1438 , G06F11/1435
摘要： The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.
摘要翻译：本发明涉及在功率循环序列之后自适应地提供数据恢复的装置，方法和/或序列，其中仅提供与数据相关联的控制块的最小更新。

10. 发明申请

US20110038127A1 MULTIPLE CHIP MODULE AND PACKAGE STACKING METHOD FOR STORAGE DEVICES 有权
标题翻译：用于存储设备的多芯片模块和封装堆叠方法
公开(公告)号：US20110038127A1
公开(公告)日：2011-02-17
申请号：US12907023
申请日：2010-10-18
申请人： Rey BRUCE , Ricardo Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
发明人： Rey BRUCE , Ricardo Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
IPC分类号： H01L25/07 , H01L21/50
CPC分类号： H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
摘要： Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
摘要翻译：堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。可以在垂直和水平方向进行扩展。

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