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1. 发明授权

US12007902B2 Configurable memory system and memory managing method thereof 有权
公开(公告)号：US12007902B2
公开(公告)日：2024-06-11
申请号：US17984189
申请日：2022-11-09
申请人： ANDES TECHNOLOGY CORPORATION
发明人： Chih-Ming Shen , Cheng-Yen Huang
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/10 , G06F2212/1024
摘要： The invention provides a configurable memory system including an interface layer, an overlay application layer, and a memory relocatable layer. The interface layer has a physical memory attribute module and a physical memory protection module. The interface layer manages memory attributes and memory security. The overlay application layer is coupled to the interface layer and executes an exception handler process to check if an overlay exception has occurred. The memory relocatable layer, coupled to the interface layer and the overlay application layer, having a plurality of resident service program within a first memory space, an overlay physical region within a second memory space, and a plurality of overlay virtual regions having application processes within a third memory space. The application processes of one of the overlay virtual regions is determined to be executed by the PMA module and is copied from the overlay virtual region to the overlay physical region by a processor.

2. 发明授权

US11687347B2 Microprocessor and method for speculatively issuing load/store instruction with non-deterministic access time using scoreboard 有权
公开(公告)号：US11687347B2
公开(公告)日：2023-06-27
申请号：US17329181
申请日：2021-05-25
申请人： ANDES TECHNOLOGY CORPORATION
发明人： Thang Minh Tran
IPC分类号： G06F9/38 , G06F9/30 , G06F13/16
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/30145 , G06F13/1668
摘要： A microprocessor and a method for issuing a load/store instruction is introduced. The microprocessor includes a decode/issue unit, a load/store queue, a scoreboard, and a load/store unit. The scoreboard includes a plurality of scoreboard entries, in which each scoreboard entry includes an unknown bit value and a count value, wherein the unknown bit value or the count value is set when instructions are issued. The decode/issue unit checks for WAR, WAW, and RAW data dependencies from the scoreboard and dispatches load/store instructions to the load/store queue with the recorded scoreboard values. The load/store queue is configured to resolve the data dependencies and dispatch the load/store instructions to the load/store unit for execution.

3. 发明授权

US11263013B2 Processor having read shifter and controlling method using the same 有权
公开(公告)号：US11263013B2
公开(公告)日：2022-03-01
申请号：US16842684
申请日：2020-04-07
申请人： ANDES TECHNOLOGY CORPORATION
发明人： Thang Minh Tran
IPC分类号： G06F9/30 , G06F1/12 , G06F1/08
摘要： A processor that includes a register file, a read shifter, a decode unit and a plurality of functional units is introduced. The register file includes a read port. The read shifter includes a plurality of shifter entries and is configured to shift out a shifter entry among the plurality of shifter entries every clock cycle. Each of the plurality of shifter entries is associated with a clock cycle and each of the plurality of shifter entries comprises a read value that indicates an availability of the read port of the register file for a read operation in the clock cycle. The decode unit is coupled to the read shifter and is configured to decode and issue an instruction based on the read values included in the plurality of shifter entries of the read shifter. The plurality of functional units is coupled to the decode unit and the register file and is configured to execute the instruction issued by the decode unit and perform the read operation to the read port of the register file.

4. 发明授权

US11188478B1 Apparatus and method for using instruction translation look-aside buffers in the branch target buffer 有权
公开(公告)号：US11188478B1
公开(公告)日：2021-11-30
申请号：US16888873
申请日：2020-06-01
申请人： ANDES TECHNOLOGY CORPORATION
发明人： Thang Minh Tran
IPC分类号： G06F12/10 , G06F12/1027
摘要： A microprocessor includes a translation look-aside buffer (TLB) having a plurality of TLB entries addressable by a branch address and having a branch target buffer (BTB), including a plurality of BTB entries addressable by the branch address. Each TLB entry includes a virtual address. Each BTB entry including a branch tag-way data and a target tag-way data. To perform a branch prediction, the BTB and TLB are accessed, where the TLB way associative data representing one of N sets of TLB entries is used to determine BTB hit or BTB miss. If BTB hit, the branch target address of the branch address may be obtained by accessing the TLB using target tag-way data in the BTB, or by using the branch page address when a same page bit in the hit BTB entry is set.

5. 发明授权

US11163582B1 Microprocessor with pipeline control for executing of instruction at a preset future time 有权
公开(公告)号：US11163582B1
公开(公告)日：2021-11-02
申请号：US16853717
申请日：2020-04-20
申请人： ANDES TECHNOLOGY CORPORATION
发明人： Thang Minh Tran
IPC分类号： G06F9/38 , G06F9/30 , G06F9/22
摘要： In the disclosure, the microprocessor resolves the conflicts in decode stage and schedules the instruction to be executed at a future time. The instruction is issued to an execution queue until the scheduled time in the future when it is dispatched to a functional unit for execution. The disclosure uses a counter for the functional unit to track when the resource is available in the future to accept the next instruction. The disclosure also tracks the future N cycles when the register file read and write ports are scheduled to read and write operand data.

6. 发明申请

US20200310974A1 PROCESSOR AND WAY PREDICTION METHOD THEREOF 审中-公开
公开(公告)号：US20200310974A1
公开(公告)日：2020-10-01
申请号：US16901015
申请日：2020-06-15
申请人： ANDES TECHNOLOGY CORPORATION
发明人： Kun-Ho Liu , Chieh-Jen Cheng , Chuan-Hua Chang , I-Cheng Kevin Chen
IPC分类号： G06F12/0862 , G06F12/0875 , G06F9/38
摘要： A processor includes a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets, each of the sets has a hot way number, at least one warm way number, and at least one confidence value corresponding to the at least one warm way number. The prediction logic circuit generates a prediction result by predicting if the at least one warm way number is an opened way. The prediction verification circuit generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. The prediction verification circuit updates the hot way number, the at least one warm way number and the at least one confidence value of the at least one warm way number according to the update information.

7. 发明授权

US10120688B2 Data processing system and method for executing block call and block return instructions 有权
公开(公告)号：US10120688B2
公开(公告)日：2018-11-06
申请号：US15352517
申请日：2016-11-15
申请人： Andes Technology Corporation
发明人： Jen-Chih Tseng , Hong-Men Su , Chuan-Hua Chang
IPC分类号： G06F9/30 , G06F9/32 , G06F9/44 , G06F9/448
摘要： A data processing system includes a control register, a program counter and a controller. The control register is used to store a level status of an execution flow and at least one return address. When the controller reads a block call instruction while a level status of the execution flow has an initial value, the controller stores a return address of the block call instruction in the control register, increments a value of the level status, and redirects the execution flow to a target address indicated by the block call instruction. When the controller reads a block return instruction and the value of the level status is not equal to the initial value, the controller decrements the value of the level status. If the value of the level status becomes equal to the initial value, the controller redirects the execution flow to the return address.

8. 发明申请

US20180054374A1 TRACE INFORMATION ENCODING APPARATUS, ENCODING METHOD THEREOF, AND READABLE COMPUTER MEDIUM 审中-公开
公开(公告)号：US20180054374A1
公开(公告)日：2018-02-22
申请号：US15241083
申请日：2016-08-19
申请人： ANDES TECHNOLOGY CORPORATION
发明人： Zhong-Ho Chen
IPC分类号： H04L12/26 , H04L29/06 , H04L12/805
CPC分类号： H04L47/365 , H04L43/04 , H04L69/22
摘要： The trace information encoding method includes: receiving events from at least one processor; generating a stream of data packets according to the events, wherein each of the data packets is composed of N data blocks, and N is a positive integer; and, writing a boundary values to each of the N data blocks.

9. 发明授权

US09183155B2 Microprocessor and method for using an instruction loop cache thereof 有权
标题翻译：微处理器及其使用指令循环缓存的方法
公开(公告)号：US09183155B2
公开(公告)日：2015-11-10
申请号：US14037395
申请日：2013-09-26
申请人： ANDES TECHNOLOGY CORPORATION
发明人： Zhong-Ho Chen , Wei-Hao Chiao
IPC分类号： G06F13/00 , G06F12/08
CPC分类号： G06F12/0875 , G06F9/30047 , G06F9/381 , Y02D10/13
摘要： A microprocessor is provided, which includes a processor core and an instruction loop cache. The processor core provides a fetch address of an instruction stream. The fetch address includes a tag and an index. The instruction loop cache receives the fetch address from the processor core. The instruction loop cache includes a cache array and a tag storage. The cache array stores multiple cache entries. Each cache entry includes a tag identification (ID). The cache array outputs the tag ID of the cache entry indicated by the index of the fetch address. The tag storage stores multiple tag values and output the tag value indicated by the tag ID output by the cache array. The instruction loop cache determines whether a cache hit or a cache miss occurs based on a bitwise comparison between the tag of the fetch address and the tag value output by the tag storage.
摘要翻译：提供了一个微处理器，它包括处理器内核和指令循环高速缓存。处理器内核提供指令流的提取地址。提取地址包括标签和索引。指令循环高速缓存从处理器内核接收提取地址。指令循环高速缓存包括高速缓存阵列和标签存储。高速缓存阵列存储多个高速缓存条目。每个缓存条目包括标签标识（ID）。高速缓存阵列输出由提取地址的索引指示的高速缓存条目的标签ID。标签存储存储多个标签值，并输出由高速缓存阵列输出的标签ID指示的标签值。指令循环高速缓存基于获取地址的标签与标签存储器输出的标签值之间的按位比较来确定是否发生高速缓存命中或高速缓存未命中。

10. 发明申请

US20150095978A1 METHOD AND APPARATUS FOR SOFTWARE-HARDWARE AUTHENTICATION OF ELECTRONIC APPARATUS 有权
标题翻译：电子设备软件硬件认证的方法与装置
公开(公告)号：US20150095978A1
公开(公告)日：2015-04-02
申请号：US14044227
申请日：2013-10-02
申请人： Andes Technology Corporation
发明人： Chi-Chang LAI , Chun-Chang YU
IPC分类号： G06F21/44
CPC分类号： G06F21/44
摘要： The present invention discloses a method for software-hardware authentication of an electronic apparatus includes receiving a challenge string (CS) from the electronic apparatus through a challenge string input port (CSIP). The challenge string is a string of trace data generated according to some operations of software running on the electronic apparatus. An authentication result for use in an authentication process for the software to authenticate a hardware unit of the electronic apparatus or for the hardware unit to authenticate the software is generated according to the string of the trace data. The authentication process is performed according to the generated authentication result.
摘要翻译：本发明公开了一种电子设备的软件硬件认证方法，包括通过挑战串输入端口（CSIP）从电子设备接收询问串（CS）。挑战串是根据在电子设备上运行的软件的一些操作生成的一串跟踪数据。根据跟踪数据的字符串生成用于认证软件的认证处理的认证结果，用于认证电子设备的硬件单元或用于硬件单元认证软件。根据生成的认证结果进行认证处理。

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