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1. 发明申请

US20050183963A1 Electrode for electrolytic processing 审中-公开
标题翻译：电解电解处理
公开(公告)号：US20050183963A1
公开(公告)日：2005-08-25
申请号：US11076067
申请日：2005-03-10
申请人： Yuzo Mori , Hidekazu Goto , Yasushi Toma
发明人： Yuzo Mori , Hidekazu Goto , Yasushi Toma
IPC分类号： B23H3/00 , C25C7/02 , C25D17/00 , C25D17/10 , C25F7/00
CPC分类号： B82Y30/00 , B23H3/00 , C25F7/00
摘要： An electrode for electrolytic processing has a conductive material and an organic compound having an ion exchange group. The organic compound is chemically bonded to a surface of the conductive material. The organic compound comprises thiol or disulfide. The ion exchange group comprises at least one of a sulfo group, a carboxyl group, a quaternary ammonium group, and an amino group. The conductive material includes at least one of gold, silver, platinum, copper, gallium arsenide, cadmium sulfide, and indium oxide (III).
摘要翻译：用于电解处理的电极具有导电材料和具有离子交换基团的有机化合物。有机化合物化学键合到导电材料的表面。有机化合物包括硫醇或二硫化物。离子交换基团包括磺基，羧基，季铵基和氨基中的至少一个。导电材料包括金，银，铂，铜，砷化镓，硫化镉和氧化铟（III）中的至少一种。

2. 发明授权

US06686619B2 Dynamic random access memory with improved contact arrangements 失效
标题翻译：动态随机存取存储器，具有改进的接触布置
公开(公告)号：US06686619B2
公开(公告)日：2004-02-03
申请号：US10137426
申请日：2002-05-03
申请人： Yoshitaka Nakamura , Hideo Aoki , Yoshikazu Ohira , Tadashi Umezawa , Satoru Yamada , Keizou Kawakita , Isamu Asano , Naoki Fukuda , Tsuyoshi Tamaru , Hidekazu Goto , Nobuyoshi Kobayashi
发明人： Yoshitaka Nakamura , Hideo Aoki , Yoshikazu Ohira , Tadashi Umezawa , Satoru Yamada , Keizou Kawakita , Isamu Asano , Naoki Fukuda , Tsuyoshi Tamaru , Hidekazu Goto , Nobuyoshi Kobayashi
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L21/28518 , H01L21/32053 , H01L21/76843 , H01L21/76855 , H01L21/76889 , H01L21/76897 , H01L27/10885 , H01L28/91 , Y10S257/908
摘要： A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.
摘要翻译：一种半导体集成电路器件及其制造方法，提供了防止在位线接触孔中的多晶硅插塞中产生起伏的优点，并且在位线和多晶硅插头的触点处横向蚀刻硅化物膜的不期望的现象是避免。在形成第一布线层时形成的位线由具有钛膜，氮化钛膜和钨膜的层叠膜制成，并且在位线和插塞的接触区域中形成含有氮或氧的硅化钛膜。含有氮或氧的硅化钛膜也形成在第一布线层和半导体衬底的接触区域中。硅化钛膜可以由含有氮或氧的硅化物膜，含有氮的硅化钴膜或氧化硅或硅化钴膜代替。

3. 发明授权

US06329681B1 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06329681B1
公开(公告)日：2001-12-11
申请号：US09215270
申请日：1998-12-18
申请人： Yoshitaka Nakamura , Hideo Aoki , Yoshikazu Ohira , Tadashi Umezawa , Satoru Yamada , Keizou Kawakita , Isamu Asano , Naoki Fukuda , Tsuyoshi Tamaru , Hidekazu Goto , Nobuyoshi Kobayashi
发明人： Yoshitaka Nakamura , Hideo Aoki , Yoshikazu Ohira , Tadashi Umezawa , Satoru Yamada , Keizou Kawakita , Isamu Asano , Naoki Fukuda , Tsuyoshi Tamaru , Hidekazu Goto , Nobuyoshi Kobayashi
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L21/28518 , H01L21/32053 , H01L21/76843 , H01L21/76855 , H01L21/76889 , H01L21/76897 , H01L27/10885 , H01L28/91 , Y10S257/908
摘要： A semiconductor integrated circuit device and a method of manufacturing such a device provides the advantages that undulations are prevented from being produced in the polycrystal silicon plugs in the bit line contact holes and that the undesired phenomenon of transversally etching the silicide film at the contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines BL formed at the time of forming a first wiring layer 18 is made of a laminate film having a titanium film 18a, a titanium nitride film 18b and a tungsten film 18c and a titanium silicide film 20 containing nitrogen or oxygen is formed in the contact areas of the bit lines BL and the plugs 19. A titanium silicide film 20 containing nitrogen or oxygen is also formed in the contact areas of the first wiring layer 18 and the semiconductor substrate 1. The titanium silicide film 20 may be replaced by a tungsten silicide film containing nitrogen or oxygen, a cobalt silicide film containing nitrogen or oxygen or a cobalt silicide film.
摘要翻译：半导体集成电路器件和这种器件的制造方法提供了这样的优点：防止在位线接触孔中的多晶硅插塞中产生起伏，并且在触点处的触点处横向蚀刻硅化物膜的不期望的现象避免了位线和多晶硅插头。在形成第一布线层18时形成的位线BL由具有钛膜18a，氮化钛膜18b和钨膜18c的层压膜和含有氮或氧的硅化钛膜20形成位线BL和插头19的接触面积。也可以在第一布线层18和半导体衬底1的接触区域中形成含有氮或氧的硅化钛膜20.硅化钛膜20可以由含有氮或氧的硅化钨膜，含有氮或氧的硅化钴膜或硅化钴膜。

4. 发明申请

US20090204375A1 Numerical simulation apparatus for time dependent schrodinger equation 失效
标题翻译：用于时间依赖薛定er方程的数值模拟装置
公开(公告)号：US20090204375A1
公开(公告)日：2009-08-13
申请号：US12310879
申请日：2007-09-07
申请人： Kikuji Hirose , Hidekazu Goto
发明人： Kikuji Hirose , Hidekazu Goto
IPC分类号： G06F17/13 , G06F17/50 , G06F19/00
CPC分类号： G06F17/5009 , G06F2217/16
摘要： To provide a numerical simulation apparatus capable of executing a numerical simulation with high speed and precision by reducing computational complexity. A numerical simulation apparatus (100) that executes a numerical simulation using a wave function which is a solution of a time dependent Schrödinger equation includes: a real time evolution calculation unit (106) that calculates a second wave function while evolving the second wave function from an initial time in increments of a predetermined time period, the second wave function being obtained by applying a central difference approximation in a real-space finite-difference method to a first wave function expressed using a propagator, and being expressed using a Bessel function; and a calculation result storage unit (108) that stores a calculation result of the second wave function obtained at each time by the time evolution calculation unit (106) while evolving the second wave function in increments of the predetermined time period.
摘要翻译：提供能够通过降低计算复杂度以高速度和精度执行数值模拟的数值模拟装置。使用作为时间相关薛定er方程的解的波函数执行数值模拟的数值模拟装置（100）包括：实时演化计算单元（106），其计算第二波函数，同时从第以预定时间段为增量的初始时间，通过将实空间有限差分法中的中心差分近似应用于使用传播者表达的第一波函数并使用贝塞尔函数表达来获得第二波函数; 以及计算结果存储单元，其存储由所述时间演算计算单元（106）在每个时间获得的所述第二波函数的计算结果，同时以所述预定时间段的增量来演进所述第二波函数。

5. 发明授权

US06215144B1 Semiconductor integrated circuit device, and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06215144B1
公开(公告)日：2001-04-10
申请号：US09236223
申请日：1999-01-25
申请人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
发明人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
IPC分类号： H01L2972
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/31604 , H01L21/76801 , H01L21/76828 , H01L21/76837 , H01L21/76843 , H01L21/76856 , H01L21/7687 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L28/40
摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
摘要翻译：在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

6. 发明授权

US07224016B2 Memory with memory cells that include a MIM type capacitor with a lower electrode made for reduced resistance at an interface with a metal film 有权
标题翻译：具有存储单元的存储器，其包括具有用于在与金属膜的界面处降低的电阻的下电极的MIM型电容器
公开(公告)号：US07224016B2
公开(公告)日：2007-05-29
申请号：US10777704
申请日：2004-02-13
申请人： Yoshitaka Nakamura , Hidekazu Goto , Isamu Asano , Mitsuhiro Horikawa , Keiji Kuroki , Hiroshi Sakuma , Kenichi Koyanagi , Tsuyoshi Kawagoe
发明人： Yoshitaka Nakamura , Hidekazu Goto , Isamu Asano , Mitsuhiro Horikawa , Keiji Kuroki , Hiroshi Sakuma , Kenichi Koyanagi , Tsuyoshi Kawagoe
IPC分类号： H01L21/8242
CPC分类号： H01L28/65 , H01L21/7687 , H01L27/10814 , H01L27/10852
摘要： A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.
摘要翻译：一种半导体器件包括各自具有形成在半导体衬底的一个主表面上的用于存储器选择的MISFET的存储单元，以及由用于存储器选择的MISFET的源极和漏极的底部电连接到下部电极的电容元件经由电容绝缘膜经由形成在下电极上的第一金属层和上电极。下部电极的底部的厚度为30nm以上。具有高电离比和高方向性的溅射（例如PCM）适于形成下电极，以使电容器的底部仅较厚。

7. 发明申请

US20050040452A1 Method for fabricating semiconductor integrated circuit 有权
公开(公告)号：US20050040452A1
公开(公告)日：2005-02-24
申请号：US10959634
申请日：2004-10-07
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L21/8242 , H01L23/522 , H01L29/76
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

8. 发明授权

US06492730B1 Method for fabricating semiconductor integrated circuit 有权
标题翻译：制造半导体集成电路的方法
公开(公告)号：US06492730B1
公开(公告)日：2002-12-10
申请号：US09480480
申请日：2000-01-11
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L2348
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
摘要翻译：根据以下步骤形成半导体器件。通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

9. 发明授权

US06399438B2 Method of manufacturing semiconductor integrated circuit device having a capacitor 有权
标题翻译：具有电容器的半导体集成电路器件的制造方法
公开(公告)号：US06399438B2
公开(公告)日：2002-06-04
申请号：US09828201
申请日：2001-04-09
申请人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
发明人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
IPC分类号： H01L218242
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/31604 , H01L21/76801 , H01L21/76828 , H01L21/76837 , H01L21/76843 , H01L21/76856 , H01L21/7687 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L28/40
摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
摘要翻译：在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

10. 发明授权

US6028360A Semiconductor integrated circuit device in which a conductive film is formed over a trap film which in turn is formed over a titanium film 失效
标题翻译：半导体集成电路器件，其中导电膜形成在捕获膜上，其又形成在钛膜上
公开(公告)号：US6028360A
公开(公告)日：2000-02-22
申请号：US106074
申请日：1998-06-29
申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
发明人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
IPC分类号： H01L21/8242 , H01L23/522 , H01L23/48 , H01L27/108
CPC分类号： H01L27/10852 , H01L23/5226 , H01L2924/0002
摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
摘要翻译：根据以下步骤形成半导体器件。通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

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