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1. 发明授权

US07817448B1 Power supply system for reducing reverse current 有权
标题翻译：用于减少反向电流的电源系统
公开(公告)号：US07817448B1
公开(公告)日：2010-10-19
申请号：US12574983
申请日：2009-10-07
申请人： Yung-Fu Lin , Chih-Hung Chen
发明人： Yung-Fu Lin , Chih-Hung Chen
IPC分类号： H02M3/335
CPC分类号： H02M3/33523
摘要： The present invention discloses a power supply system for reducing reverse current, the system comprising a primary side circuit, for receiving alternating current; a transformer circuit, for transforming voltage; a secondary side rectifier circuit, for rectifying voltage; a secondary side filter circuit, for filtering voltage and providing direct current to a device; a first voltage division circuit, for providing a first voltage division signal; a switch circuit, for deciding the conducting condition based on the first voltage division signal and a reference voltage signal; a second voltage division circuit, for providing a second voltage division signal; and a control circuit, for deciding the charging condition based on the second voltage division signal; wherein the second voltage division circuit comprising a rectifier component and a filter component, for rectifying and filtering the source of the second voltage division signal.
摘要翻译：本发明公开了一种用于减少反向电流的电源系统，该系统包括用于接收交流电流的初级侧电路; 用于转换电压的变压器电路; 用于整流电压的二次侧整流电路; 二次侧滤波电路，用于过滤电压并向器件提供直流电; 第一分压电路，用于提供第一分压信号; 开关电路，用于基于第一分压信号和参考电压信号来决定导通条件; 第二分压电路，用于提供第二分压信号; 以及控制电路，用于基于所述第二分压信号来确定所述充电条件; 其中所述第二分压电路包括整流器组件和滤波器组件，用于对所述第二分压信号的源进行整流和滤波。

2. 发明授权

US08416105B2 ADC calibration apparatus 有权
标题翻译： ADC校准装置
公开(公告)号：US08416105B2
公开(公告)日：2013-04-09
申请号：US13029754
申请日：2011-02-17
申请人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
发明人： Fang-Shi Jordan Lai , Chin-Hao Chang , Manoj M. Mhala , Hsu-Feng Hsueh , Yung-Fu Lin , Cheng Yen Weng
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/361
摘要： An analog-to-digital (ADC) calibration apparatus comprises a calibration buffer, a comparator and a digital calibration block. Each reference voltage is sent to a track-and-hold amplifier as well as the calibration buffer. The comparator compares the output from the track-and-hold amplifier and the output from the calibration buffer and generates a binary number. Based upon a successive approximation method, the digital calibration block finds a correction voltage for ADC offset and nonlinearity compensation. By employing the ADC calibration apparatus, each reference voltage can be calibrated and the corresponding correction voltage can be used to modify the reference voltage during an ADC process.
摘要翻译：模数（ADC）校准装置包括校准缓冲器，比较器和数字校准块。每个参考电压被发送到跟踪和保持放大器以及校准缓冲器。比较器比较跟踪和保持放大器的输出和校准缓冲区的输出，并生成二进制数。基于逐次逼近方法，数字校准块找到用于ADC偏移和非线性补偿的校正电压。通过采用ADC校准装置，可以校准每个参考电压，并且可以使用相应的校正电压来修改ADC过程中的参考电压。

3. 发明授权

US08279097B2 Background calibration of analog-to-digital converters 有权
标题翻译：模数转换器的背景校准
公开(公告)号：US08279097B2
公开(公告)日：2012-10-02
申请号：US12775104
申请日：2010-05-06
申请人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
发明人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
IPC分类号： H03M1/10
CPC分类号： H03M1/1042 , H03M1/1004 , H03M1/168
摘要： A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.
摘要翻译：一种操作模数转换器（ADC）的方法包括提供包括多个级的ADC，每个级分别包括运算放大器，以及分别包括第一输入端和第二输入端的第一电容器和第二电容器。第一电容器和第二电容器中的每一个包括连接到运算放大器的相同输入端的附加端。该方法还包括执行多个信号转换。每个信号转换在多级中的一个级的放大阶段中包括将第一电压施加到多级中的一级的第一输入端，从两个不同电压随机选择第二电压; 以及将所述第二电压施加到所述多个级中的所述一个级的所述第二输入端。

4. 发明申请

US20110012763A1 Background Calibration of Analog-to-Digital Converters 有权
标题翻译：模数转换器的背景校准
公开(公告)号：US20110012763A1
公开(公告)日：2011-01-20
申请号：US12775104
申请日：2010-05-06
申请人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
发明人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
IPC分类号： H03M1/10 , H03M1/12 , H03M1/34
CPC分类号： H03M1/1042 , H03M1/1004 , H03M1/168
摘要： A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.
摘要翻译：一种操作模数转换器（ADC）的方法包括提供包括多个级的ADC，每个级分别包括运算放大器，以及分别包括第一输入端和第二输入端的第一电容器和第二电容器。第一电容器和第二电容器中的每一个包括连接到运算放大器的相同输入端的附加端。该方法还包括执行多个信号转换。每个信号转换在多级中的一个级的放大阶段中包括将第一电压施加到多级中的一级的第一输入端，从两个不同电压随机选择第二电压; 以及将所述第二电压施加到所述多个级中的所述一个级的所述第二输入端。

5. 发明授权

US08928508B2 ADC calibration 有权
标题翻译： ADC校准
公开(公告)号：US08928508B2
公开(公告)日：2015-01-06
申请号：US13526147
申请日：2012-06-18
申请人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
发明人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
IPC分类号： H03M1/10 , H03M1/36
CPC分类号： H03M1/1009 , H03M1/1004 , H03M1/365
摘要： An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated.
摘要翻译：包括连接到ADC的多个比较器的模数转换器（ADC）。 ADC还包括连接到多个比较器中的每一个的第一对端子和第二对端子。 ADC还包括耦合到第一对端子中的每一个的第一对开关和耦合到第二对端子中的每一个的第二对开关，其中第一和第二对开关被配置为在正常操作和校准配置。如果对应的比较器被配置为校准，则比较器对应的比较器被配置为正常运行。

6. 发明授权

US08228221B2 Method and apparatus for calibrating sigma-delta modulator 有权
标题翻译：用于校准Σ-Δ调制器的方法和装置
公开(公告)号：US08228221B2
公开(公告)日：2012-07-24
申请号：US12891952
申请日：2010-09-28
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin , Manoj M. Mhala , Tao Wen Chung , Chin-Hao Chang
IPC分类号： H03M3/02
CPC分类号： H03M3/38 , H03M3/414
摘要： In a method of converting an analog signal to digital format, an analog input signal is received and processed using sigma-delta modulation to provide a first digital signal that represents the analog input signal in digital format and to provide a second digital signal that represents a first error introduced during the sigma-delta modulation. A second error that is error introduced during the sigma-delta modulation is estimated. A pre-correction signal is determined based on the first and second digital signals. A difference between the estimated second error and the pre-correction digital signal is determined to provide a digital output signal representing the analog input signal in digital format. An error correction element operable to adjust the digital output signal based on the analog input signal, the digital output signal, and the second digital signal is controlled.
摘要翻译：在将模拟信号转换为数字格式的方法中，使用Σ-Δ调制接收和处理模拟输入信号，以提供表示数字格式的模拟输入信号的第一数字信号，并提供表示第在Σ-Δ调制期间引入的第一个误差。估计在Σ-Δ调制期间引入误差的第二个误差。基于第一和第二数字信号确定预校正信号。确定估计的第二误差和预校正数字信号之间的差异以提供表示数字格式的模拟输入信号的数字输出信号。控制基于模拟输入信号，数字输出信号和第二数字信号来调整数字输出信号的纠错元件。

7. 发明申请

US20100164766A1 DAC Variation-Tracking Calibration 有权
标题翻译： DAC变化跟踪校准
公开(公告)号：US20100164766A1
公开(公告)日：2010-07-01
申请号：US12347014
申请日：2008-12-31
申请人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
发明人： Fang-Shi Jordan Lai , Kuo-Ming Wang , Hsu-Feng Hsueh , Cheng Yen Weng , Yung-Fu Lin
IPC分类号： H03M1/10
CPC分类号： H03M1/1057
摘要： A method of calibrating a digital-to-analog converter (DAC) is provided. The DAC includes a least-significant bit (LSB) block, and dummy LSB block adjacent to the LSB block. The DAC has a most-significant bit (MSB) block, which includes MSB thermometer macros. The method includes measuring the dummy LSB block to obtain a dummy LSB sum; and calibrating the MSB block so that each of the MSB thermometer macros provides a substantially same current as the dummy LSB sum.
摘要翻译：提供了一种校准数模转换器（DAC）的方法。 DAC包括最低有效位（LSB）块和与LSB块相邻的虚拟LSB块。 DAC具有最高有效位（MSB）块，其中包含MSB温度计宏。该方法包括测量虚拟LSB块以获得虚拟LSB和; 并校准MSB块，使得每个MSB温度计宏提供与虚拟LSB总和大致相同的电流。

8. 发明授权

US08692571B2 Apparatus and method for measuring degradation of CMOS VLSI elements 有权
标题翻译：用于测量CMOS VLSI元件退化的装置和方法
公开(公告)号：US08692571B2
公开(公告)日：2014-04-08
申请号：US13183521
申请日：2011-07-15
申请人： Fang-Shi Jordan Lai , Chih-Cheng Lu , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Manoj M. Mhala
发明人： Fang-Shi Jordan Lai , Chih-Cheng Lu , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Manoj M. Mhala
IPC分类号： G01R31/00 , G01R31/319
CPC分类号： G01R31/31924 , G01R31/2642
摘要： The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.
摘要翻译：集成电路的可靠性是根据样品金属氧化物半导体（MOS）器件的可操作特性推断的，该器件可以切换地耦合到漏极/源极偏置和栅极输入电压，这些标称电压和电流条件会提高应力并引起临时或永久性降解，例如热载流子注入（HCI），偏置温度不稳定性（BTI，NBTI，PBTI），时间依赖介电击穿（TDDB）。所测试的MOS器件（优选同时或同时测试的PMOS和NMOS器件）被配置为向具有级联的反相器级的环形振荡器供电的电流源，从而改变振荡器频率作为应力的影响的量度在被测设备上，但不会升高施加到逆变器级的应力。

9. 发明授权

US08493259B2 Pipeline analog-to-digital converter 有权
标题翻译：管道模数转换器
公开(公告)号：US08493259B2
公开(公告)日：2013-07-23
申请号：US13311639
申请日：2011-12-06
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Chih-Cheng Lu , Manoj M. Mhala , Yung-Fu Lin
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Chih-Cheng Lu , Manoj M. Mhala , Yung-Fu Lin
IPC分类号： H03M1/34
CPC分类号： H03M1/1014 , H03M1/0695 , H03M1/168 , H03M1/44
摘要： A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.
摘要翻译：流水线模数转换器包括第一，第二和第三对比较器。第一对比较器将输入电压与第一正参考电压和第一负参考电压进行比较。第二对比较器将输入电压与第二正参考电压和第二负参考电压进行比较。第一和第二对比较器的每个比较器向编码器输出数字信号。第三对比较器将输入电压与第三正参考电压和第三负参考电压进行比较，比较器将输入电压与地比较。比较器和第三对比较器对的每个比较器被配置为将相应的数字信号输出到编码器。乘法数模转换器输出基于输入电压的电压，来自编码器的输出和随机数发生器的输出。

10. 发明申请

US20120212361A1 SWITCHED-CAPACITOR CIRCUIT WITH LOW SIGNAL DEGRADATION 有权
标题翻译：具有低信号降级的开关电容电路
公开(公告)号：US20120212361A1
公开(公告)日：2012-08-23
申请号：US13030862
申请日：2011-02-18
申请人： Fang-Shi Lai , Manoj M. Mhala , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng
发明人： Fang-Shi Lai , Manoj M. Mhala , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng
IPC分类号： H03M3/02 , H03K5/22
CPC分类号： H03K5/24 , H03M3/352 , H03M3/45 , H03M3/452
摘要： A switched-capacitor circuit is disclosed. The switched-capacitor circuit includes a comparator having a first and second input, a first and second sampling capacitor, and a first and second switching circuitry. The first switching circuitry charges the first and second sampling capacitor with an input signal. The second switching circuitry selectively couples the first sampling capacitor with a reference voltage and selectively couples the second sampling capacitor and the first and second input of the comparator to a common voltage. The comparator performs a compare of the input signals against the reference voltage, and outputs a signal.
摘要翻译：公开了一种开关电容器电路。开关电容器电路包括具有第一和第二输入，第一和第二采样电容器以及第一和第二开关电路的比较器。第一开关电路用输入信号对第一和第二采样电容器充电。第二开关电路选择性地将第一采样电容器与参考电压耦合，并且将第二采样电容器和比较器的第一和第二输入端选择性地耦合到公共电压。比较器执行输入信号与参考电压的比较，并输出信号。

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