专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100219485A1 FORMATION OF RAISED SOURCE/DRAIN STUCTURES IN NFET WITH EMBEDDED SIGE IN PFET 有权
标题翻译：在PFET中嵌入信号的NFET中形成上升的源/漏极结构
公开(公告)号：US20100219485A1
公开(公告)日：2010-09-02
申请号：US12780962
申请日：2010-05-17
申请人： Yung Fu CHONG , Zhijiong LUO , Joo Chan KIM , Judson Robert HOLT
发明人： Yung Fu CHONG , Zhijiong LUO , Joo Chan KIM , Judson Robert HOLT
IPC分类号： H01L27/092 , H01L27/088
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.
摘要翻译：用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。我们在凹槽中形成PFET嵌入式源极/漏极应力器。我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

2. 发明申请

US20120001228A1 METHOD TO CONTROL SOURCE/DRAIN STRESSOR PROFILES FOR STRESS ENGINEERING 有权
标题翻译：控制应力工程源/排水压力分布的方法
公开(公告)号：US20120001228A1
公开(公告)日：2012-01-05
申请号：US13229773
申请日：2011-09-12
申请人： Yung Fu CHONG , Zhijiong LUO , Judson Robert HOLT
发明人： Yung Fu CHONG , Zhijiong LUO , Judson Robert HOLT
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
摘要翻译：应变通道晶体管结构的示例性实施例包括以下：包含具有第一自然晶格常数的第一半导体材料的应变通道区域; 覆盖在应变通道区上的栅介质层; 覆盖所述栅介质层的栅电极; 以及源极区域和漏极区域，其与所述应变通道区域相邻地邻近，所述源极区域和漏极区域中的一个或两个由包含第二半导体材料的应力区域构成，所述第二半导体材料具有不同于所述第一自然晶格常数的第二自然晶格常数 ; 应力区域具有掺杂剂杂质和/或应力诱导分子的分级浓度。另一个示例性实施例是形成渐变杂质或应力诱导分子应力嵌入S / D区域的过程，由此S / D应力器的位置/轮廓不由凹槽深度/轮廓限定。

3. 发明申请

US20110223737A1 IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS 有权
标题翻译：用于设备应用的信号外观下的嵌入式D区域的损伤控制
公开(公告)号：US20110223737A1
公开(公告)日：2011-09-15
申请号：US13113107
申请日：2011-05-23
申请人： Jin Ping LIU , Judson Robert HOLT
发明人： Jin Ping LIU , Judson Robert HOLT
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/4238 , H01L29/66636 , H01L29/7833
摘要： Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.
摘要翻译：本发明的一些示例性实施例包括用于和半导体结构的方法，包括：源极/漏极区，栅极电介质，栅电极，沟道区的MOS晶体管; 碳掺杂的SiGe区域，其在沟道区域上施加应力，由此碳掺杂SiGe区域在随后的热处理之后在沟道区域上保持应力/应变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式