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1. 发明授权

US08810025B2 Reinforcement structure for flip-chip packaging 有权
标题翻译：倒装芯片封装的加固结构
公开(公告)号：US08810025B2
公开(公告)日：2014-08-19
申请号：US13050125
申请日：2011-03-17
申请人： Yu-Wen Liu , Ching-Jung Yang , Hsien-Wei Chen , Hsin-Yu Pan , Chao-Wen Shih
发明人： Yu-Wen Liu , Ching-Jung Yang , Hsien-Wei Chen , Hsin-Yu Pan , Chao-Wen Shih
IPC分类号： H01L23/14 , H01L23/12
CPC分类号： H01L23/49822 , H01L23/49827 , H01L23/562 , H01L24/16 , H01L24/81 , H01L2224/1132 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/13116 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/73204 , H01L2224/81191 , H01L2224/8121 , H01L2224/81815 , H01L2224/83102 , H01L2924/1305 , H01L2924/13091 , H01L2924/1461 , H01L2924/00014 , H01L2924/0665 , H01L2924/00
摘要： The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region.
摘要翻译：本公开提供了载体基板，包括载体基板的装置以及将载体基板结合到芯片的方法。示例性器件包括具有芯片区域和外围区域的载体衬底和结合到载体衬底的芯片区域的芯片。载体衬底包括嵌入在周边区域内的加强结构。

2. 发明申请

US20120235303A1 REINFORCEMENT STRUCTURE FOR FLIP-CHIP PACKAGING 有权
标题翻译：片芯包装加固结构
公开(公告)号：US20120235303A1
公开(公告)日：2012-09-20
申请号：US13050125
申请日：2011-03-17
申请人： Yu-Wen Liu , Ching-Jung Yang , Hsien-Wei Chen , Hsin-Yu Pan , Chao-Wen Shih
发明人： Yu-Wen Liu , Ching-Jung Yang , Hsien-Wei Chen , Hsin-Yu Pan , Chao-Wen Shih
IPC分类号： H01L23/498 , H01L21/50 , H01L23/48
CPC分类号： H01L23/49822 , H01L23/49827 , H01L23/562 , H01L24/16 , H01L24/81 , H01L2224/1132 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/13116 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/73204 , H01L2224/81191 , H01L2224/8121 , H01L2224/81815 , H01L2224/83102 , H01L2924/1305 , H01L2924/13091 , H01L2924/1461 , H01L2924/00014 , H01L2924/0665 , H01L2924/00
摘要： The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region.
摘要翻译：本公开提供了载体基板，包括载体基板的装置以及将载体基板结合到芯片的方法。示例性器件包括具有芯片区域和外围区域的载体衬底和结合到载体衬底的芯片区域的芯片。载体基板包括嵌入在周边区域内的加强结构。

3. 发明授权

US09117831B2 Seal ring structure for integrated circuit chips 有权
标题翻译：集成电路芯片的密封环结构
公开(公告)号：US09117831B2
公开(公告)日：2015-08-25
申请号：US13004261
申请日：2011-01-11
申请人： Ching-Jung Yang , Yu-Wen Liu , Michael Shou-Ming Tong , Hsien-Wei Chen , Chung-Ying Yang , Tsung-Yuan Yu
发明人： Ching-Jung Yang , Yu-Wen Liu , Michael Shou-Ming Tong , Hsien-Wei Chen , Chung-Ying Yang , Tsung-Yuan Yu
IPC分类号： H01L23/00 , H01L23/58
CPC分类号： H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.
摘要翻译：半导体器件包括具有电路区域和密封环区域的衬底。密封圈区域围绕电路区域。密封环结构设置在密封环区域的上方。密封环结构具有在第一部分上方的第一部分和第二部分。第一部分具有宽度W1，第二部分具有宽度W2。宽度W1小于宽度W2。

4. 发明授权

US08610267B2 Reducing delamination between an underfill and a buffer layer in a bond structure 有权
公开(公告)号：US08610267B2
公开(公告)日：2013-12-17
申请号：US12840900
申请日：2010-07-21
申请人： Ching-Jung Yang , Chang-Pin Huang , Tzuan-Horng Liu , Michael Shou-Ming Tong , Ying-Ju Chen , Tung-Liang Shao , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii
发明人： Ching-Jung Yang , Chang-Pin Huang , Tzuan-Horng Liu , Michael Shou-Ming Tong , Ying-Ju Chen , Tung-Liang Shao , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii
IPC分类号： H01L23/48
CPC分类号： H01L24/81 , H01L21/563 , H01L23/3114 , H01L23/3142 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/93 , H01L25/0657 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05554 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/11464 , H01L2224/11849 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81424 , H01L2224/81439 , H01L2224/81447 , H01L2224/81464 , H01L2224/93 , H01L2224/94 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/15788 , H01L2224/11 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.

5. 发明申请

US20110284843A1 Probe Pad On A Corner Stress Relief Region In A Semiconductor Chip 有权
标题翻译：探针垫在A半导体芯片中的拐角应力消除区域
公开(公告)号：US20110284843A1
公开(公告)日：2011-11-24
申请号：US13198408
申请日：2011-08-04
申请人： Hsien-Wei Chen , Chung-Ying Yang , Ying-Ju Chen , Shih-Wei Liang , Ching-Jung Yang
发明人： Hsien-Wei Chen , Chung-Ying Yang , Ying-Ju Chen , Shih-Wei Liang , Ching-Jung Yang
IPC分类号： H01L23/528
CPC分类号： H01L27/0203 , H01L22/34 , H01L23/585 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05553 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.
摘要翻译：半导体芯片包括角部应力消除（CSR）区域。增强的结构将密封环结构的侧面连接到包围CSR区域。被测设备（DUT）结构设置在CSR区域上。一组探针垫结构设置在CSR区域上。探针焊盘结构中的两个电连接到DUT结构。

6. 发明授权

US08237160B2 Probe pad on a corner stress relief region in a semiconductor chip 有权
标题翻译：在半导体芯片的拐角应力释放区域的探针垫
公开(公告)号：US08237160B2
公开(公告)日：2012-08-07
申请号：US13198408
申请日：2011-08-04
申请人： Hsien-Wei Chen , Chung-Ying Yang , Ying-Ju Chen , Shih-Wei Liang , Ching-Jung Yang
发明人： Hsien-Wei Chen , Chung-Ying Yang , Ying-Ju Chen , Shih-Wei Liang , Ching-Jung Yang
IPC分类号： H01L23/58
CPC分类号： H01L27/0203 , H01L22/34 , H01L23/585 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05553 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.
摘要翻译：半导体芯片包括角部应力消除（CSR）区域。增强的结构将密封环结构的侧面连接到包围CSR区域。被测设备（DUT）结构设置在CSR区域上。一组探针垫结构设置在CSR区域上。探针焊盘结构中的两个电连接到DUT结构。

7. 发明申请

US20120092033A1 MEASUREMENT OF ELECTRICAL AND MECHANICAL CHARACTERISTICS OF LOW-K DIELECTRIC IN A SEMICONDUCTOR DEVICE 有权
标题翻译：低K介质在半导体器件中的电气和机械特性的测量
公开(公告)号：US20120092033A1
公开(公告)日：2012-04-19
申请号：US12903984
申请日：2010-10-13
申请人： Tung-Liang Shao , Shih-Wei Liang , Ying-Ju Chen , Ching-Jung Yang , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
发明人： Tung-Liang Shao , Shih-Wei Liang , Ying-Ju Chen , Ching-Jung Yang , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： G01R31/00 , G01R27/00 , G01R29/26
CPC分类号： G01R31/2648 , G01R31/002 , G01R31/2644 , G01R31/2884 , H01L22/34 , H01L2224/13
摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.
摘要翻译：提供了一种用于测试未封装的半导体晶片的测试结构。测试结构包括耦合到半导体晶片的互连结构的施力部件。力施加部件可操作以向半导体晶片施加力。测试结构还包括耦合到互连结构的第一和第二测试部分。第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

8. 发明申请

US20120018875A1 Reducing Delamination Between an Underfill and a Buffer layer in a Bond Structure 有权
标题翻译：减少粘结结构中底层填料和缓冲层之间的分层
公开(公告)号：US20120018875A1
公开(公告)日：2012-01-26
申请号：US12840900
申请日：2010-07-21
申请人： Ching-Jung Yang , Chang-Pin Huang , Tzuan-Horng Liu , Michael Shou-Ming Tong , Ying-Ju Chen , Tung-Liang Shao , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii
发明人： Ching-Jung Yang , Chang-Pin Huang , Tzuan-Horng Liu , Michael Shou-Ming Tong , Ying-Ju Chen , Tung-Liang Shao , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii
IPC分类号： H01L23/498
CPC分类号： H01L24/81 , H01L21/563 , H01L23/3114 , H01L23/3142 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/93 , H01L25/0657 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05554 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/11464 , H01L2224/11849 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81424 , H01L2224/81439 , H01L2224/81447 , H01L2224/81464 , H01L2224/93 , H01L2224/94 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/15788 , H01L2224/11 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.
摘要翻译：模具包括金属焊盘，钝化层和钝化层上的图案化缓冲层。图案化缓冲层包括彼此分离的多个离散部分。在图案化缓冲层的开口和钝化层中的开口上形成凸块下冶金（UBM）。在UBM上形成电耦合的金属凸块。

9. 发明授权

US08618827B2 Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device 有权
标题翻译：半导体器件中低K电介质的电气和机械特性的测量
公开(公告)号：US08618827B2
公开(公告)日：2013-12-31
申请号：US12903984
申请日：2010-10-13
申请人： Tung-Liang Shao , Shih-Wei Liang , Ying-Ju Chen , Ching-Jung Yang , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
发明人： Tung-Liang Shao , Shih-Wei Liang , Ying-Ju Chen , Ching-Jung Yang , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2648 , G01R31/002 , G01R31/2644 , G01R31/2884 , H01L22/34 , H01L2224/13
摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.
摘要翻译：提供了一种用于测试未封装的半导体晶片的测试结构。测试结构包括耦合到半导体晶片的互连结构的施力部件。力施加部件可操作以向半导体晶片施加力。测试结构还包括耦合到互连结构的第一和第二测试部分。第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

10. 发明授权

US08445911B2 Active device array substrate 有权
标题翻译：有源器件阵列衬底
公开(公告)号：US08445911B2
公开(公告)日：2013-05-21
申请号：US12770737
申请日：2010-04-30
申请人： Ching-Jung Yang , Ke-Chih Chang , Kuo-Yu Huang , Yu-Cheng Chen
发明人： Ching-Jung Yang , Ke-Chih Chang , Kuo-Yu Huang , Yu-Cheng Chen
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00
CPC分类号： G02F1/136213 , G02F1/133371 , G02F1/133504 , G02F1/133555 , G02F1/136227 , H01L27/1255
摘要： An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices.
摘要翻译：提供了包括衬底，扫描线，数据线，有源器件，第一介电层，公共线，第二电介质层，图案化导电层，第三电介质层和像素电极的有源器件阵列衬底。有源器件的至少一部分电连接到扫描线和数据线。第一介电层覆盖扫描线，数据线和有源器件。公共线设置在第一电介质层上。第二介电层覆盖公共线和第一介电层。图案化导电层设置在第二介电层上。第三电介质层覆盖图案化的导电层和第二介电层。像素电极设置在第三电介质层上并电连接到图案化导电层和有源器件。

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