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1. 发明授权

US06294456B1 Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule 有权
标题翻译：使用光刻胶在顶部金属层预填孔眼的方法，以防止钝化损坏，即使是严格的顶级金属规则
公开(公告)号：US06294456B1
公开(公告)日：2001-09-25
申请号：US09200589
申请日：1998-11-27
申请人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
发明人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
IPC分类号： H01L214763
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps are performed. Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap. Then strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap. Next, form a blanket, second photoresist layer above the blanket layer. The gap has a neck with a width from about 200 Å to about 500 Å and the gap has a deep, pocket-like cross-section with a width from about 500 Å to about 1,200 Å below the narrow neck. Partial stripping of the first photoresist layer, which follows, is performed by an etching process including wet and dry processing.
摘要翻译：这是在形成在覆盖氮化硅层的间隙上形成的层上形成的光致抗蚀剂层的表面的平面化方法，该覆盖氮化硅层又在半导体器件的表面上的SOG层之间的金属化形成在键孔上方。执行以下步骤。在覆盖氮化硅之上形成一个毯子，第一个光刻胶层，由间隙引起损坏的表面。然后剥离第一光致抗蚀剂层，留下间隙中的第一光致抗蚀剂层的残留部分。接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。间隙具有宽度从大约至大约500埃的颈部，并且间隙具有深的袋状横截面，宽度在窄的颈部以下从大约500到大约1,200埃。通过包括湿法和干法处理的蚀刻工艺进行随后的第一光致抗蚀剂层的部分剥离。

2. 发明授权

US6100116A Method to form a protected metal fuse 失效
标题翻译：形成保护金属保险丝的方法
公开(公告)号：US6100116A
公开(公告)日：2000-08-08
申请号：US99144
申请日：1998-06-18
申请人： Yu-Hua Lee , James Wu , Jenn Ming Huang , Cheng-Yeh Shih , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James Wu , Jenn Ming Huang , Cheng-Yeh Shih , Min-Hsiung Chiang
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A method for forming protection layers completely around a metal fuse to protect the metal fuse 74A and metal lines 74B from moisture corrosion from fuse opening and micro-cracks in dielectric layers. The invention surrounds the fuse on all sides with two protection layers: a bottom protection layer 70 and a top protection layer 78. The top protection layer 78 is formed over the fuse metal, the sidewalls of the metal fuse and the bottom protection layer 70. The protection layers 70 78 of the invention form a moisture proof seal structure around the metal fuse 74A and protect the metal fuse 74A and metal lines 74B from moisture and contaminates.
摘要翻译：一种用于在金属保险丝周围完全形成保护层的方法，用于保护金属保险丝74A和金属线74B免受保险丝开口的湿度腐蚀和电介质层中的微裂纹。本发明在所有侧面上具有两个保护层的保险丝：底部保护层70和顶部保护层78.顶部保护层78形成在熔丝金属，金属熔断器的侧壁和底部保护层70上。本发明的保护层70 78在金属熔断器74A周围形成防潮密封结构，并且保护金属熔断器74A和金属线74B免受潮湿和污染。

3. 发明授权

US06600228B2 Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule 有权
标题翻译：顶部金属水平的锁孔预填充光致抗蚀剂，以防止钝化损坏，即使是严重的顶级金属规则
公开(公告)号：US06600228B2
公开(公告)日：2003-07-29
申请号：US09929676
申请日：2001-08-15
申请人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
发明人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
IPC分类号： H01L214763
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresist layer was formed above the blanket silicon nitride to fill the damage to the surface caused by the hole. Then the first photoresist layer was stripped leaving a residual portion of the first photoresist layer filling the hole. Next, a blanket, second photoresist layer was formed above the blanket layer. The hole has a neck with a width from about 200 Å to about 500 Å and the hole has a deep, pocket-like gap with a cross-section with a width from about 500 Å to about 1200 Å below the narrow neck.
摘要翻译：光致抗蚀剂层的平坦化表面形成在形成在覆盖层中的孔的上方的层上，保形的氮化硅层，其又形成在半导体器件的表面上的SOG层之间的金属化中的锁孔上方。在覆盖氮化硅上方形成毯状的第一光致抗蚀剂层，以填充由孔引起的对表面的损伤。然后剥离第一光致抗蚀剂层，留下填充孔的第一光致抗蚀剂层的残留部分。接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。该孔具有宽度从大约至大约500埃的颈部，并且该孔具有深的袋状间隙，其横截面的宽度从窄到90度到大约在1200度。

4. 发明授权

US06436763B1 Process for making embedded DRAM circuits having capacitor under bit-line (CUB) 有权
标题翻译：在位线（CUB）下制造具有电容器的嵌入式DRAM电路的工艺
公开(公告)号：US06436763B1
公开(公告)日：2002-08-20
申请号：US09498738
申请日：2000-02-07
申请人： Jenn Ming Huang , Yu-Hua Lee , Cheng Ming Wu
发明人： Jenn Ming Huang , Yu-Hua Lee , Cheng Ming Wu
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811 , H01L27/10894 , H01L28/84 , H01L28/90
摘要： A method for fabricating capacitor-under-bit line (CUB) DRAMs with logic circuits is achieved. CUB are better than capacitor-over-bit line (COB) DRAM circuits because of reduced contact aspect ratios, but CUB require patterning the capacitor top plate over the capacitor rough topography while providing openings to bit line contacts between closely spaced capacitors. A bottom antireflecting coating (BARC) is used in a first method; a non-conform PECVD oxide is used in a second method to make reliable high aspect ratio openings between the capacitors. The BARC is deposited to fill the space between capacitors. A photo-resist layer with improved uniformity is then deposited over the BARC and exposed and developed to form an etch mask with improved resolution for the capacitor top plate. The BARC is plasma etched, and the polysilicon plate is patterned. In the second method a non-conformal PECVD oxide is deposited that is thicker on the top of the capacitors than in the narrow space between capacitors. The PECVD oxide is anisotropically etched back to form self-aligned openings over the bit line contacts, and openings are etched in the polysilicon capacitor top plate aligned over the bit line contact openings. A photoresist etch mask is then used to complete the patterning of the top plate.
摘要翻译：实现了具有逻辑电路的用于制造电容器下位线（CUB）DRAM的方法。 CUB比电容器位线（COB）DRAM电路更好，因为接触宽高比减小，但是CUB需要在电容器粗糙的形状图上形成电容器顶板，同时为紧密间隔的电容器之间的位线接触提供开口。在第一种方法中使用底部抗反射涂层（BARC）; 在第二种方法中使用不合格的PECVD氧化物，以在电容器之间形成可靠的高纵横比开口。 BARC存放以填补电容器之间的空间。然后将具有改善的均匀性的光致抗蚀剂层沉积在BARC上，并暴露和显影以形成具有改进的用于电容器顶板的分辨率的蚀刻掩模。 BARC被等离子体蚀刻，多晶硅板被图案化。在第二种方法中，沉积在电容器顶部比在电容器之间的狭窄空间中更厚的非共形PECVD氧化物。 PECVD氧化物被各向异性地回蚀以在位线触点上形成自对准的开口，并且在多晶硅电容器顶板上蚀刻开口，在位线接触开口上对齐。然后使用光致抗蚀剂蚀刻掩模来完成顶板的图案化。

5. 发明授权

US6042999A Robust dual damascene process 失效
标题翻译：坚固的双镶嵌工艺
公开(公告)号：US6042999A
公开(公告)日：2000-03-28
申请号：US73952
申请日：1998-05-07
申请人： Cheng-Tung Lin , Yu-Hua Lee , Jenn Ming Huang , Cheng-Ming Wu
发明人： Cheng-Tung Lin , Yu-Hua Lee , Jenn Ming Huang , Cheng-Ming Wu
IPC分类号： G03F7/00 , H01L21/027 , H01L21/768 , G03F7/26
CPC分类号： H01L21/76808 , G03F7/0035 , H01L21/0276
摘要： A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In the first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need of an etch-stop layer for the dual damascene process of this invention.
摘要翻译：公开了一种稳健的双镶嵌工艺，其中通过在形成镶嵌导电线开口之前通过填充具有保护材料的接触或通孔开口来保护衬底中的子结构免受由镶嵌工艺中所需的多次蚀刻所造成的损伤具有分隔下电介质层和上电介质层的蚀刻停止层的结构。在第一实施例中，在通过蚀刻形成上导电线开口之前，保护材料部分地从到达底层结构的开孔中去除。在第二实施例中，在通过蚀刻形成上导电线开口的同时去除孔中的保护材料。在第三个实施例中，应用所公开的工艺，而不需要用于本发明的双镶嵌工艺的蚀刻停止层。

6. 发明授权

US06274426B1 Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure 有权
标题翻译：自对准接触工艺为冠状动态随机存取存储器电容器结构
公开(公告)号：US06274426B1
公开(公告)日：2001-08-14
申请号：US09257830
申请日：1999-02-25
申请人： Yu-Hua Lee , James (Cheng-Ming) Wu , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James (Cheng-Ming) Wu , Min-Hsiung Chiang
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/31116 , H01L21/3212 , H01L21/76802 , H01L21/76897 , H01L27/10855 , H01L28/91
摘要： A process for fabricating a crown shaped, capacitor structure, in a SAC opening, featuring a silicon nitride spacer, located on the walls of a bottom portion of the SAC opening, has been developed. The process features forming a SAC opening in a thick silicon oxide layer, then repairing, or filling, seams or voids, that may be present in the thick silicon oxide layer, at the perimeter of the SAC opening, via formation of a silicon nitride spacer on the sides of the SAC opening. Subsequent processing features: the isotropic removal of a top portion of the silicon nitride spacer; the formation of a polysilicon storage node structure, in the SAC opening; and the recessing of a top portion of the thick silicon oxide layer, resulting in exposure of additional polysilicon storage node, surface area.
摘要翻译：已经开发了一种用于制造位于SAC开口的底部的壁上的具有氮化硅间隔物的SAC开口中的冠状电容器结构的方法。该工艺特征是在厚的氧化硅层中形成SAC开口，然后通过形成氮化硅间隔物在SAC开口的周边处形成可能存在于厚氧化硅层中的或者填充接缝或空隙在SAC开幕的两边。随后的处理特征：氮化硅间隔物的顶部的各向同性去除; 形成多晶硅存储节点结构，在SAC开放; 并且厚的氧化硅层的顶部凹陷，导致额外的多晶硅存储节点的曝光，表面积。

7. 发明授权

US5989954A Method for forming a cylinder capacitor in the dram process 失效
标题翻译：在戏剧过程中形成圆筒电容器的方法
公开(公告)号：US5989954A
公开(公告)日：1999-11-23
申请号：US35056
申请日：1998-03-05
申请人： Yu-Hua Lee , Jenn Ming Huang
发明人： Yu-Hua Lee , Jenn Ming Huang
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for fabricating a cylindrical capacitor is described. Semiconductor device structures, including a capacitor node contact region, are formed on a semiconductor substrate. A first insulating layer is deposited over the device structures and planarized. A silicon nitride layer and then a second insulating layer are deposited over the first insulating layer. A contact opening having a first width is etched through the insulating layers and the silicon nitride layer to the capacitor node contact region. A photoresist mask is formed over the second insulating layer having a mask opening over the contact opening wherein the mask opening has a second width wider than the first width and wherein photoresist residue remains at the bottom of the contact opening. A second opening is etched in the second insulating layer corresponding to the mask opening wherein the photoresist residue protects the semiconductor substrate within the contact opening during etching. The photoresist mask and residue are removed. A first layer of polysilicon is deposited to fill the contact opening. The first polysilicon layer overlying the second insulating layer is polished away to form the bottom electrode of the capacitor. The second insulating layer is removed. A capacitor dielectric layer is deposited over the silicon nitride layer and the first polysilicon layer. A second polysilicon layer is deposited overlying the capacitor dielectric layer to form the top electrode of the capacitor.
摘要翻译：描述了一种用于制造圆柱形电容器的方法。包括电容器节点接触区域的半导体器件结构形成在半导体衬底上。第一绝缘层沉积在器件结构上并且被平坦化。在第一绝缘层上沉积氮化硅层，然后沉积第二绝缘层。具有第一宽度的接触开口通过绝缘层和氮化硅层蚀刻到电容器节点接触区域。在具有在接触开口上方的掩模开口的第二绝缘层上形成光致抗蚀剂掩模，其中掩模开口具有比第一宽度宽的第二宽度，并且其中光致抗蚀剂残留物保留在接触开口的底部。在对应于掩模开口的第二绝缘层中蚀刻第二开口，其中光致抗蚀剂残留物在蚀刻期间保护接触开口内的半导体衬底。去除光致抗蚀剂掩模和残留物。沉积第一层多晶硅以填充接触开口。覆盖第二绝缘层的第一多晶硅层被抛光以形成电容器的底部电极。去除第二绝缘层。在氮化硅层和第一多晶硅层上沉积电容器介电层。沉积在电容器介电层上的第二多晶硅层以形成电容器的顶部电极。

8. 发明授权

US5854119A Robust method of forming a cylinder capacitor for DRAM circuits 失效
标题翻译：形成用于DRAM电路的圆柱电容器的坚固的方法
公开(公告)号：US5854119A
公开(公告)日：1998-12-29
申请号：US058794
申请日：1998-04-13
申请人： James Wu , Yu-Hua Lee , Jenn Ming Huang
发明人： James Wu , Yu-Hua Lee , Jenn Ming Huang
IPC分类号： H01L21/02 , H01L21/311 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L21/31116 , H01L28/40
摘要： A method of forming a capacitor for DRAM or other circuits is described which avoids the problem of weak spots or gaps forming between a polysilicon contact plug and the first capacitor plate. A layer of first dielectric is formed on a substrate, A layer of second dielectric is formed on the layer of first dielectric. A layer of third dielectric is formed on the layer of second dielectric. A first hole is formed in the first, second, and third dielectrics exposing a contact region of the substrate. The first hole is then filled with a protective material and a second hole is formed in the layer of third dielectric using the layer of second dielectric as an etch stop. The first hole lies within the periphery of the second hole. The protective material prevents re-deposition of the third dielectric. The remaining protective material is then removed and a layer of conducting material is formed on the top surface of the layer of third dielectric, the sidewalls of the second hole, the sidewalls of the first hole, and the contact region of the substrate thereby forming a first capacitor plate.
摘要翻译：描述了形成用于DRAM或其他电路的电容器的方法，其避免了在多晶硅接触插塞和第一电容器板之间形成的弱点或间隙的问题。在基板上形成第一电介质层。在第一电介质层上形成第二电介质层。在第二电介质层上形成第三电介质层。在暴露基板的接触区域的第一，第二和第三电介质中形成第一孔。然后用保护材料填充第一孔，并且使用第二电介质层作为蚀刻停止件在第三电介质层中形成第二孔。第一个孔位于第二个孔的周围。保护材料防止第三电介质的再沉积。然后去除剩余的保护材料，并且在第三电介质层的顶表面，第二孔的侧壁，第一孔的侧壁和衬底的接触区域上形成导电材料层，从而形成第一电容器板。

9. 发明授权

US06020236A Method to form capacitance node contacts with improved isolation in a DRAM process 有权
标题翻译：在DRAM工艺中形成具有改进的隔离的电容节点触点的方法
公开(公告)号：US06020236A
公开(公告)日：2000-02-01
申请号：US257723
申请日：1999-02-25
申请人： Yu-Hua Lee , James Wu , Wen-Chuan Chiang , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James Wu , Wen-Chuan Chiang , Min-Hsiung Chiang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method to form capacitance node contacts with improved isolation in a DRAM process is described. An isolation layer is formed on a semiconductor substrate. A first contact hole is formed and filled with a polysilicon plug and the top surface of the isolation layer and of the polysilicon plug are polished to a planar surface. A first interpoly isolation layer is deposited. A stopping layer is deposited. A capping layer is deposited. A first polysilicon layer is deposited. The first polysilicon layer is etched to form features. A second interpoly isolation layer is deposited. The second interpoly isolation layer is planarized. The second contact hole is etched through the second interpoly isolation layer and the capping layer. The exposed first polysilicon material is etched back to the vertical sides of the second contact hole. The stopping layer and the first interpoly isolation layer are etched through to the top surface of the polysilicon plug. A lining layer of silicon nitride is deposited and etched to remain only on the vertical interior surfaces of the second contact hole. A second polysilicon layer is deposited to fill the second contact hole. The second polysilicon layer and the second interpoly isolation layer are planarized. The fabrication of the integrated circuit device is completed.
摘要翻译：描述了在DRAM处理中形成具有改进的隔离的电容节点触点的方法。在半导体衬底上形成隔离层。形成第一接触孔并填充多晶硅插塞，并且隔离层和多晶硅插塞的顶表面被抛光到平坦表面。沉积第一间隔隔离层。沉积停止层。沉积覆盖层。沉积第一多晶硅层。第一多晶硅层被蚀刻以形成特征。沉积第二个互隔离层。第二间隔隔离层被平坦化。第二接触孔被蚀刻穿过第二多晶硅隔离层和封盖层。暴露的第一多晶硅材料被回蚀刻到第二接触孔的垂直侧。停止层和第一互隔离层被蚀刻到多晶硅插塞的顶表面。沉积和蚀刻氮化硅的内衬层以仅保留在第二接触孔的垂直内表面上。沉积第二多晶硅层以填充第二接触孔。第二多晶硅层和第二多晶硅隔离层被平坦化。完成集成电路器件的制造。

10. 发明授权

US06555435B2 Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids 有权
公开(公告)号：US06555435B2
公开(公告)日：2003-04-29
申请号：US10087070
申请日：2002-03-01
申请人： Ming-Hsiung Chiang , James Wu , Yu-Hua Lee
发明人： Ming-Hsiung Chiang , James Wu , Yu-Hua Lee
IPC分类号： H01L2336
CPC分类号： H01L21/76831 , H01L21/76897
摘要： A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask. A passivation layer is deposited overlying the conductive layer and the dielectric layer. The integrated circuit device is completed.

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