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1. 发明授权

US06020236A Method to form capacitance node contacts with improved isolation in a DRAM process 有权
标题翻译：在DRAM工艺中形成具有改进的隔离的电容节点触点的方法
公开(公告)号：US06020236A
公开(公告)日：2000-02-01
申请号：US257723
申请日：1999-02-25
申请人： Yu-Hua Lee , James Wu , Wen-Chuan Chiang , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James Wu , Wen-Chuan Chiang , Min-Hsiung Chiang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method to form capacitance node contacts with improved isolation in a DRAM process is described. An isolation layer is formed on a semiconductor substrate. A first contact hole is formed and filled with a polysilicon plug and the top surface of the isolation layer and of the polysilicon plug are polished to a planar surface. A first interpoly isolation layer is deposited. A stopping layer is deposited. A capping layer is deposited. A first polysilicon layer is deposited. The first polysilicon layer is etched to form features. A second interpoly isolation layer is deposited. The second interpoly isolation layer is planarized. The second contact hole is etched through the second interpoly isolation layer and the capping layer. The exposed first polysilicon material is etched back to the vertical sides of the second contact hole. The stopping layer and the first interpoly isolation layer are etched through to the top surface of the polysilicon plug. A lining layer of silicon nitride is deposited and etched to remain only on the vertical interior surfaces of the second contact hole. A second polysilicon layer is deposited to fill the second contact hole. The second polysilicon layer and the second interpoly isolation layer are planarized. The fabrication of the integrated circuit device is completed.
摘要翻译：描述了在DRAM处理中形成具有改进的隔离的电容节点触点的方法。在半导体衬底上形成隔离层。形成第一接触孔并填充多晶硅插塞，并且隔离层和多晶硅插塞的顶表面被抛光到平坦表面。沉积第一间隔隔离层。沉积停止层。沉积覆盖层。沉积第一多晶硅层。第一多晶硅层被蚀刻以形成特征。沉积第二个互隔离层。第二间隔隔离层被平坦化。第二接触孔被蚀刻穿过第二多晶硅隔离层和封盖层。暴露的第一多晶硅材料被回蚀刻到第二接触孔的垂直侧。停止层和第一互隔离层被蚀刻到多晶硅插塞的顶表面。沉积和蚀刻氮化硅的内衬层以仅保留在第二接触孔的垂直内表面上。沉积第二多晶硅层以填充第二接触孔。第二多晶硅层和第二多晶硅隔离层被平坦化。完成集成电路器件的制造。

2. 发明授权

US6100116A Method to form a protected metal fuse 失效
标题翻译：形成保护金属保险丝的方法
公开(公告)号：US6100116A
公开(公告)日：2000-08-08
申请号：US99144
申请日：1998-06-18
申请人： Yu-Hua Lee , James Wu , Jenn Ming Huang , Cheng-Yeh Shih , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James Wu , Jenn Ming Huang , Cheng-Yeh Shih , Min-Hsiung Chiang
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A method for forming protection layers completely around a metal fuse to protect the metal fuse 74A and metal lines 74B from moisture corrosion from fuse opening and micro-cracks in dielectric layers. The invention surrounds the fuse on all sides with two protection layers: a bottom protection layer 70 and a top protection layer 78. The top protection layer 78 is formed over the fuse metal, the sidewalls of the metal fuse and the bottom protection layer 70. The protection layers 70 78 of the invention form a moisture proof seal structure around the metal fuse 74A and protect the metal fuse 74A and metal lines 74B from moisture and contaminates.
摘要翻译：一种用于在金属保险丝周围完全形成保护层的方法，用于保护金属保险丝74A和金属线74B免受保险丝开口的湿度腐蚀和电介质层中的微裂纹。本发明在所有侧面上具有两个保护层的保险丝：底部保护层70和顶部保护层78.顶部保护层78形成在熔丝金属，金属熔断器的侧壁和底部保护层70上。本发明的保护层70 78在金属熔断器74A周围形成防潮密封结构，并且保护金属熔断器74A和金属线74B免受潮湿和污染。

3. 发明授权

US06294456B1 Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule 有权
标题翻译：使用光刻胶在顶部金属层预填孔眼的方法，以防止钝化损坏，即使是严格的顶级金属规则
公开(公告)号：US06294456B1
公开(公告)日：2001-09-25
申请号：US09200589
申请日：1998-11-27
申请人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
发明人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
IPC分类号： H01L214763
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps are performed. Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap. Then strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap. Next, form a blanket, second photoresist layer above the blanket layer. The gap has a neck with a width from about 200 Å to about 500 Å and the gap has a deep, pocket-like cross-section with a width from about 500 Å to about 1,200 Å below the narrow neck. Partial stripping of the first photoresist layer, which follows, is performed by an etching process including wet and dry processing.
摘要翻译：这是在形成在覆盖氮化硅层的间隙上形成的层上形成的光致抗蚀剂层的表面的平面化方法，该覆盖氮化硅层又在半导体器件的表面上的SOG层之间的金属化形成在键孔上方。执行以下步骤。在覆盖氮化硅之上形成一个毯子，第一个光刻胶层，由间隙引起损坏的表面。然后剥离第一光致抗蚀剂层，留下间隙中的第一光致抗蚀剂层的残留部分。接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。间隙具有宽度从大约至大约500埃的颈部，并且间隙具有深的袋状横截面，宽度在窄的颈部以下从大约500到大约1,200埃。通过包括湿法和干法处理的蚀刻工艺进行随后的第一光致抗蚀剂层的部分剥离。

4. 发明授权

US06403416B1 Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) 有权
标题翻译：制造用于动态随机存取存储器（DRAM）的双缸电容器结构的方法
公开(公告)号：US06403416B1
公开(公告)日：2002-06-11
申请号：US09226279
申请日：1999-01-07
申请人： Kuo Ching Huang , Yu-Hua Lee , James (Cheng-Ming) Wu , Wen-Chuan Chiang
发明人： Kuo Ching Huang , Yu-Hua Lee , James (Cheng-Ming) Wu , Wen-Chuan Chiang
IPC分类号： H01L218242
CPC分类号： H01L28/91
摘要： A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.
摘要翻译：描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。在热磷酸中除去第一和第二Si 3 N 4层。电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。

5. 发明授权

US06103455A Method to form a recess free deep contact 失效
标题翻译：形成无凹陷深层接触的方法
公开(公告)号：US06103455A
公开(公告)日：2000-08-15
申请号：US73947
申请日：1998-05-07
申请人： Kuo Ching Huang , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
发明人： Kuo Ching Huang , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
IPC分类号： H01L21/768 , G03F7/26
CPC分类号： H01L21/76876 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/7688
摘要： A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over the hard mask layer 30. The hard mask layer 30 is etched through the contact photoresist opening 39 to form a contact hard mask opening 41 exposing the dielectric layer 20. The dielectric layer 20 is etched using a high density plasma etch process using the contact photoresist layer 36 and the hard mask layer 30 as an etch mask forming a contact hole 40 in the dielectric layer 20. The contact photoresist layer 36 is removed. A metal layer 50 is formed filling the contact hole 40 and covering over the hard mask layer 30. The metal layer 50 is etched back forming a plug 52 filling the contact hole 40. Now, the hard mask layer 30 is removed. The removal of the hard mask 30 after the metal layer 50 deposition: (a) prevents the contact hole 40 from being contaminated from photoresist and other contamination formed during the hard mask 30 removal steps; and (b) creates a plug 52 that does not have a recess.
摘要翻译：通过在半导体结构10上形成电介质层20来形成深度接触的方法。主要的一点是在形成插头52之后去除硬掩模30。在电介质层20上形成硬掩模层30.在硬掩模层30之上形成接触光刻胶层36.硬掩模层30通过接触光致抗蚀剂开口39蚀刻以形成接触硬掩模开口41，电介质层20.使用接触光致抗蚀剂层36和硬掩模层30作为在电介质层20中形成接触孔40的蚀刻掩模的高密度等离子体蚀刻工艺来蚀刻电介质层20.接触光致抗蚀剂层36是删除。形成填充接触孔40并覆盖在硬掩模层30上的金属层50.金属层50被回蚀，形成填充接触孔40的插塞52.现在，去除硬掩模层30。在金属层50沉积之后去除硬掩模30：（a）防止接触孔40在硬掩模30去除步骤期间被光致抗蚀剂和其它污染物污染; 和（b）产生不具有凹部的插头52。

6. 发明授权

US06194234B1 Method to evaluate hemisperical grain (HSG) polysilicon surface 有权
标题翻译：评估半晶粒（HSG）多晶硅表面的方法
公开(公告)号：US06194234B1
公开(公告)日：2001-02-27
申请号：US09324925
申请日：1999-06-04
申请人： Kuo-Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang , Yu-Hua Lee
发明人： Kuo-Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang , Yu-Hua Lee
IPC分类号： G01R3126
CPC分类号： H01L22/12
摘要： A new method based on measuring the weight of a wafer (on which the layer of HSG has been deposited) before (W1) and after (W2) the surface of the HSG layer is coated with a layer of either photoresist or SOG. The difference delta W=W2−W1 provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG. This new method can also be based on measuring the weight W of rejected or dropped PR or SOG after the surface of the HSG layer has been coated with a layer of either photoresist or SOG. The weight of the rejected or dropped PR or SOG also provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG.
摘要翻译：基于测量在HSG层的表面之前（W1）和之后（W2）的晶片（其上沉积了HSG的层）的重量的新方法涂覆有光致抗蚀剂或SOG层。差值ΔW= W2-W1提供HSG沉积层的表面的粗糙度或平滑度的指标。这种新方法也可以基于测量在HSG层的表面已经涂覆有光致抗蚀剂或SOG层之后的被拒绝或掉落的PR或SOG的重量W。拒收或掉落的PR或SOG的重量也提供HSG沉积层的表面的粗糙度或平滑度的指标。

7. 发明授权

US06274426B1 Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure 有权
标题翻译：自对准接触工艺为冠状动态随机存取存储器电容器结构
公开(公告)号：US06274426B1
公开(公告)日：2001-08-14
申请号：US09257830
申请日：1999-02-25
申请人： Yu-Hua Lee , James (Cheng-Ming) Wu , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James (Cheng-Ming) Wu , Min-Hsiung Chiang
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/31116 , H01L21/3212 , H01L21/76802 , H01L21/76897 , H01L27/10855 , H01L28/91
摘要： A process for fabricating a crown shaped, capacitor structure, in a SAC opening, featuring a silicon nitride spacer, located on the walls of a bottom portion of the SAC opening, has been developed. The process features forming a SAC opening in a thick silicon oxide layer, then repairing, or filling, seams or voids, that may be present in the thick silicon oxide layer, at the perimeter of the SAC opening, via formation of a silicon nitride spacer on the sides of the SAC opening. Subsequent processing features: the isotropic removal of a top portion of the silicon nitride spacer; the formation of a polysilicon storage node structure, in the SAC opening; and the recessing of a top portion of the thick silicon oxide layer, resulting in exposure of additional polysilicon storage node, surface area.
摘要翻译：已经开发了一种用于制造位于SAC开口的底部的壁上的具有氮化硅间隔物的SAC开口中的冠状电容器结构的方法。该工艺特征是在厚的氧化硅层中形成SAC开口，然后通过形成氮化硅间隔物在SAC开口的周边处形成可能存在于厚氧化硅层中的或者填充接缝或空隙在SAC开幕的两边。随后的处理特征：氮化硅间隔物的顶部的各向同性去除; 形成多晶硅存储节点结构，在SAC开放; 并且厚的氧化硅层的顶部凹陷，导致额外的多晶硅存储节点的曝光，表面积。

8. 发明授权

US06600228B2 Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule 有权
标题翻译：顶部金属水平的锁孔预填充光致抗蚀剂，以防止钝化损坏，即使是严重的顶级金属规则
公开(公告)号：US06600228B2
公开(公告)日：2003-07-29
申请号：US09929676
申请日：2001-08-15
申请人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
发明人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
IPC分类号： H01L214763
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresist layer was formed above the blanket silicon nitride to fill the damage to the surface caused by the hole. Then the first photoresist layer was stripped leaving a residual portion of the first photoresist layer filling the hole. Next, a blanket, second photoresist layer was formed above the blanket layer. The hole has a neck with a width from about 200 Å to about 500 Å and the hole has a deep, pocket-like gap with a cross-section with a width from about 500 Å to about 1200 Å below the narrow neck.
摘要翻译：光致抗蚀剂层的平坦化表面形成在形成在覆盖层中的孔的上方的层上，保形的氮化硅层，其又形成在半导体器件的表面上的SOG层之间的金属化中的锁孔上方。在覆盖氮化硅上方形成毯状的第一光致抗蚀剂层，以填充由孔引起的对表面的损伤。然后剥离第一光致抗蚀剂层，留下填充孔的第一光致抗蚀剂层的残留部分。接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。该孔具有宽度从大约至大约500埃的颈部，并且该孔具有深的袋状间隙，其横截面的宽度从窄到90度到大约在1200度。

9. 发明授权

US07482278B1 Key-hole free process for high aspect ratio gap filling with reentrant spacer 有权
标题翻译：无缝隙工艺，用于高长宽比间隙填充可重入间隔
公开(公告)号：US07482278B1
公开(公告)日：2009-01-27
申请号：US09247974
申请日：1999-02-11
申请人： Tze-Liang Ying , James (Cheng-Ming) Wu , Yu-Hua Lee , Wen-Chuan Chiang
发明人： Tze-Liang Ying , James (Cheng-Ming) Wu , Yu-Hua Lee , Wen-Chuan Chiang
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31056 , H01L21/76837
摘要： A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern, further leaving a deposition of HDP-oxide on the top surface of the poly pattern. The profile of the holes within the poly pattern in such that the final layer of PE-oxide or PE-TEOS is deposited without resulting in the formation of keyholes in this latter layer.
摘要翻译：一种沉积PE氧化物或PE-TEOS的新方法。在多晶硅图案上提供HDP氧化物。对沉积的HDP-氧化物进行回蚀刻，沉积一层等离子体增强的SiN。该PE-SiN被回蚀刻，留下多边形图案的侧壁上的SiN间隔物，进一步在多晶型图案的顶表面上留下HDP氧化物。多晶型图案中的孔的轮廓使得沉积最终的聚乙烯氧化物层或PE-TEOS层，而不会在后一层中形成键槽。

10. 发明授权

US06187659B1 Node process integration technology to improve data retention for logic based embedded dram 有权
标题翻译：节点过程集成技术，以提高基于逻辑的嵌入式电脑的数据保留
公开(公告)号：US06187659B1
公开(公告)日：2001-02-13
申请号：US09368861
申请日：1999-08-06
申请人： Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
发明人： Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Ming Wu , Yu-Hua Lee
IPC分类号： H01L214763
CPC分类号： H01L27/10855 , H01L21/28525 , H01L21/76877 , H01L21/76885 , H01L21/76897
摘要： A new method is provided to create a gradated dopant concentration in the contact plug of DRAM devices whereby a high dopant concentration is present at the bottom of the plug and a low dopant concentration is present at the top of the plug. Two layers of dielectric are deposited; the upper layer serves as a layer to adjust the dopant concentration in the lower layer. This adjustment is done by Rapid Thermal anneal of both layers of dielectric. After the dopant concentration has been adjusted, the upper layer of dielectric is removed and the upper section of the contact node is formed using lightly doped poly. The high dopant concentration at the bottom of the contact plug results in low contact resistance between the plug and the underlying silicon substrate. A low dopant concentration at the top surface of the contact plug results in low oxidation of the surface of the plug.
摘要翻译：提供了一种新的方法来在DRAM器件的接触插塞中产生渐变的掺杂剂浓度，由此在插塞的底部存在高的掺杂剂浓度，并且在插头的顶部存在低的掺杂剂浓度。沉积两层电介质; 上层用作调整下层中的掺杂剂浓度的层。这种调整是通过两层电介质的快速热退火进行的。在调整掺杂剂浓度之后，去除电介质的上层，并且使用轻掺杂的多晶形成接触节点的上部。接触插塞底部的高掺杂剂浓度导致插头和底层硅衬底之间的低接触电阻。在接触塞顶表面的低掺杂剂浓度导致插塞表面的低氧化。

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