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1. 发明申请

US20120020179A1 METHOD AND APPARATUS FOR WORD LINE DECODER LAYOUT 有权
标题翻译：字线解码器布局的方法和装置
公开(公告)号：US20120020179A1
公开(公告)日：2012-01-26
申请号：US12839490
申请日：2010-07-20
申请人： You-Cheng XIAO , Hong-Chen CHENG , Chung-Ji LU , Cheng Hung LEE , Jung-Hsuan CHEN , Li-Chun TIEN
发明人： You-Cheng XIAO , Hong-Chen CHENG , Chung-Ji LU , Cheng Hung LEE , Jung-Hsuan CHEN , Li-Chun TIEN
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C11/413
摘要： A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.
摘要翻译：字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。字线解码器还包括耦合到每个主输入线的本地解码线。字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。集群解码线耦合到解码线。字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

2. 发明申请

US20120206953A1 MEMORY EDGE CELL 有权
标题翻译：记忆边缘细胞
公开(公告)号：US20120206953A1
公开(公告)日：2012-08-16
申请号：US13025872
申请日：2011-02-11
申请人： Hong-Chen CHENG , Ming-Yi LEE , Kuo-Hua PAN , Jung-Hsuan CHEN , Li-Chun TIEN , Cheng Hung LEE , Hung-Jen LIAO
发明人： Hong-Chen CHENG , Ming-Yi LEE , Kuo-Hua PAN , Jung-Hsuan CHEN , Li-Chun TIEN , Cheng Hung LEE , Hung-Jen LIAO
IPC分类号： G11C5/06 , H01L25/00
CPC分类号： G11C5/06 , G11C5/147 , G11C5/148 , G11C11/417
摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
摘要翻译：电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

3. 发明申请

US20120032293A1 EDGE DEVICES LAYOUT FOR IMPROVED PERFORMANCE 有权
标题翻译：边缘设备布局改善性能
公开(公告)号：US20120032293A1
公开(公告)日：2012-02-09
申请号：US12851702
申请日：2010-08-06
申请人： Yen-Huei CHEN , Jung-Hsuan CHEN , Shao-Yu CHOU , Hung-Jen LIAO , Li-Chun TIEN
发明人： Yen-Huei CHEN , Jung-Hsuan CHEN , Shao-Yu CHOU , Hung-Jen LIAO , Li-Chun TIEN
IPC分类号： H01L27/08 , H01L21/822
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/823425 , H01L21/823481 , H01L27/0207 , H01L29/66628 , H01L29/7848
摘要： A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.
摘要翻译：字线驱动器包括具有沿半导体衬底的第一方向延伸的长度的有源区。多个指状物形成在有源区域的上表面上。多个指状物中的每一个具有在第二方向上延伸的长度，并且形成具有有效区域的一部分的MOS晶体管。第一虚设结构设置在多个指状物的外部之一和半导体衬底的边缘之间。第一虚拟结构包括至少部分地设置在有效区域的一部分上的部分。

4. 发明申请

US20110291200A1 INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20110291200A1
公开(公告)日：2011-12-01
申请号：US13086186
申请日：2011-04-13
申请人： Ali KESHAVARZI , Ta-Pen GUO , Helen Shu-Hui CHANG , Hsiang-Jen TSENG , Shyue-Shyh LIN , Lee-Chung LU , Chung-Cheng WU , Li-Chun TIEN , Jung-Chan YANG , Shu-Min CHEN , Min CAO , Yung-Chin HOU
发明人： Ali KESHAVARZI , Ta-Pen GUO , Helen Shu-Hui CHANG , Hsiang-Jen TSENG , Shyue-Shyh LIN , Lee-Chung LU , Chung-Cheng WU , Li-Chun TIEN , Jung-Chan YANG , Shu-Min CHEN , Min CAO , Yung-Chin HOU
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

5. 发明申请

US20130087932A1 INTEGRATED CIRCUITS AND METHODS OF DESIGNING THE SAME 有权
标题翻译：集成电路及其设计方法
公开(公告)号：US20130087932A1
公开(公告)日：2013-04-11
申请号：US13267310
申请日：2011-10-06
申请人： Lee-Chung LU , Li-Chun TIEN , Hui-Zhong ZHUANG , Mei-Hui HUANG
发明人： Lee-Chung LU , Li-Chun TIEN , Hui-Zhong ZHUANG , Mei-Hui HUANG
IPC分类号： H01L29/41 , G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068 , G06F17/5077 , H01L27/11807 , H01L2027/11875 , H01L2027/11885
摘要： A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.
摘要翻译：设计集成电路的方法包括在第一标准单元中部署有效区域。至少一个栅电极被路由，与第一标准单元中的有效区重叠。至少一个金属线结构被路由，与第一标准单元中的有效区重叠。至少一个金属线结构基本上平行于栅电极。第一电源轨道基本上正交于第一标准单元中的至少一个金属线结构。第一电力轨与至少一个金属线结构重叠。第一动力轨具有与至少一个金属线结构相邻的平坦边缘。第一连接插头部署在第一电力轨道与第一标准单元中的至少一个金属线结构重叠的区域处。

6. 发明申请

US20120240088A1 SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS 有权
标题翻译：设计集成电路的系统与方法
公开(公告)号：US20120240088A1
公开(公告)日：2012-09-20
申请号：US13047419
申请日：2011-03-14
申请人： Ta-Pen GUO , Li-Chun TIEN , Shyue-Shyh LIN , Mei-Hui HUANG
发明人： Ta-Pen GUO , Li-Chun TIEN , Shyue-Shyh LIN , Mei-Hui HUANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505 , G06F2217/72
摘要： A method of designing an integrated circuit includes defining at least one dummy layer covering at least one of a portion of a first metallic layer and a portion of a second metallic layer of an integrated circuit. The second metallic layer is disposed over the first metallic layer. The first metallic layer, the second metallic layer and a gate electrode of the integrated circuit have a same routing direction. A logical operation is performed to a file corresponding to the at least one of the portion of the first metallic layer and the portion of the second metallic layer covered by the dummy layer so as to size at least one of the portion of the first metallic layer and the portion of the second metallic layer.
摘要翻译：设计集成电路的方法包括限定覆盖第一金属层的一部分和集成电路的第二金属层的一部分中的至少一个的至少一个虚设层。第二金属层设置在第一金属层上。集成电路的第一金属层，第二金属层和栅电极具有相同的布线方向。对与第一金属层的部分的至少一个和由虚设层覆盖的第二金属层的部分相对应的文件执行逻辑操作，以便使第一金属层的至少一个部分和第二金属层的部分。

7. 发明申请

US20140332971A1 METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路的方法和布局
公开(公告)号：US20140332971A1
公开(公告)日：2014-11-13
申请号：US14341130
申请日：2014-07-25
申请人： Hsiang-Jen TSENG , Ting-Wei CHIANG , Wei-Yu CHEN , Ruei-Wun SUN , Hung-Jung TSENG , Shun Li CHEN , Li-Chun TIEN
发明人： Hsiang-Jen TSENG , Ting-Wei CHIANG , Wei-Yu CHEN , Ruei-Wun SUN , Hung-Jung TSENG , Shun Li CHEN , Li-Chun TIEN
IPC分类号： G06F17/50 , H01L23/482
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5072 , H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.
摘要翻译：集成电路布局包括P型有源区和N型有源区，以及多个树干。集成电路布局还包括连接到P型有源区的第一金属连接; 以及连接到N型有源区的第二金属连接。多个树干的每个中继线与第一金属连接和第二金属连接电连接。多个树干的每个树干基本上垂直于第一金属连接和第二金属连接。多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度。

8. 发明申请

US20140210014A1 METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION 有权
标题翻译：在标准电池配置中用金属化电阻形成集成电路的方法和装置
公开(公告)号：US20140210014A1
公开(公告)日：2014-07-31
申请号：US13779783
申请日：2013-02-28
申请人： Wei Yu MA , Bo-Ting CHEN , Ting Yu CHEN , Kuo-Ji CHEN , Li-Chun TIEN
发明人： Wei Yu MA , Bo-Ting CHEN , Ting Yu CHEN , Kuo-Ji CHEN , Li-Chun TIEN
IPC分类号： H01L27/02
CPC分类号： H01L27/0288 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/0248 , H01L27/0629 , H01L27/11807 , H01L28/20 , H01L28/24
摘要： An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.
摘要翻译：集成电路包括半导体器件层，其包括在栅电极线之间具有固定栅电极间距的标准单元配置和在标准单元配置的固定栅电极间距之间由金属形成的电阻。在一个实施例中，集成电路可以是具有由金属形成的电阻器的交叉域标准单元的充电器件模型（CDM）静电放电（ESD）保护电路。制造集成电路的方法包括：形成由栅电极间距分开的多个栅极电极线，以形成芯标准电池器件，在栅电极间距内施加至少第一金属层以形成电阻器的一部分，以及施加至少第二金属层以耦合到第一金属层以形成电阻器的另一部分。

9. 发明申请

US20140195997A1 METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路的方法和布局
公开(公告)号：US20140195997A1
公开(公告)日：2014-07-10
申请号：US13778912
申请日：2013-02-27
申请人： Hsiang-Jen TSENG , Ting-Wei CHIANG , Wei-Yu CHEN , Ruei-Wun SUN , Hung-Jung TSENG , Shun Li CHEN , Li-Chun TIEN
发明人： Hsiang-Jen TSENG , Ting-Wei CHIANG , Wei-Yu CHEN , Ruei-Wun SUN , Hung-Jung TSENG , Shun Li CHEN , Li-Chun TIEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5072 , H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks.
摘要翻译：集成电路布局包括P型有源区，N型有源区，第一金属连接，第二金属连接和多个树干。多个树干基本并排地形成并且彼此平行。第一金属连接基本上设置在P型有源区上，并且与P型有源区中的PMOS晶体管的漏极区域电连接。第二金属连接基本上设置在N型有源区上，并且与N型有源区中的NMOS晶体管的漏区电连接。多个树干电连接并且基本上垂直于第一金属连接和第二金属连接。多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度，并且布置成位于两组树干之间。

10. 发明申请

US20120331426A1 CELL ARCHITECTURE AND METHOD 有权
标题翻译：细胞结构和方法
公开(公告)号：US20120331426A1
公开(公告)日：2012-12-27
申请号：US13207506
申请日：2011-08-11
申请人： Lee-Chung LU , Li-Chun TIEN , Shyue-Shyh LIN , Zhe-Wei JIANG
发明人： Lee-Chung LU , Li-Chun TIEN , Shyue-Shyh LIN , Zhe-Wei JIANG
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G06F17/504 , G06F17/5072 , H01L2924/0002 , H01L2924/00
摘要： A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks.
摘要翻译：一种方法包括：选择存储在非瞬态计算机可读存储介质中的单元，将多个单元布置在半导体器件的模型上，以及基于半导体器件的模型为半导体器件创建掩模。电池根据设计规则设计，其中第一电源连接通孔满足以下组的标准：i）第一电源连接通孔与第二电源连接通路间隔开距离大于阈值距离，使得可以通过单光刻单蚀刻工艺制造单元，或者ii）第一电源连接通孔耦合到第一和第二基本平行的导线，其延伸沿着直接相邻的轨道。

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