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1. 发明授权

US5568068A Buffer circuit for regulating driving current 失效
标题翻译：用于调节驱动电流的缓冲电路
公开(公告)号：US5568068A
公开(公告)日：1996-10-22
申请号：US534114
申请日：1995-09-26
申请人： Yoshiyuki Ota , Ichiro Tomioka , Eiji Murakami
发明人： Yoshiyuki Ota , Ichiro Tomioka , Eiji Murakami
IPC分类号： H03K19/0175 , G11C11/409 , H03F1/56 , H03K19/003
CPC分类号： H03K19/00323
摘要： A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied. A buffer circuit with driving current adjusting function of the present invention comprises a buffer circuit which is controlled by a control signal for supplying a most appropriate driving current to a load; a load detecting circuit for detecting a phase difference between an input signal and an output signal of the buffer circuit and for outputting voltage corresponding to the phase difference, a control signal generating circuit for generating a signal which controls the driving current of the buffer circuit in response to an output signal of the load detecting circuit, the control signal controls so that the driving current of buffer circuit is increased when delay time of buffer circuit becomes long and the driving current of buffer circuit is decreased when delay time becomes short.
摘要翻译：提供具有驱动电流调节功能的缓冲电路，其可以根据要施加驱动电流的系统自动将缓冲器的驱动电流特性设置为最合适的值。具有本发明的驱动电流调节功能的缓冲电路包括缓冲电路，该缓冲电路由用于向负载提供最合适的驱动电流的控制信号控制; 负载检测电路，用于检测输入信号和缓冲电路的输出信号之间的相位差并输出与相位差相对应的电压;控制信号发生电路，用于产生控制缓冲电路的驱动电流的信号响应于负载检测电路的输出信号，当延迟时间变短时，缓冲电路的延迟时间变长，缓冲电路的驱动电流减小时，控制信号进行控制，使得缓冲电路的驱动电流增加。

2. 发明申请

US20110073439A1 Aligning and Feeding Device 审中-公开
标题翻译：对准和送料装置
公开(公告)号：US20110073439A1
公开(公告)日：2011-03-31
申请号：US12994636
申请日：2009-06-02
申请人： Yoshiyuki Ota , Tomoyuki Shimoguchi , Takahiro Takigawa
发明人： Yoshiyuki Ota , Tomoyuki Shimoguchi , Takahiro Takigawa
IPC分类号： B65G47/14
CPC分类号： B65G47/1457 , B65G47/24 , B65G47/525
摘要： An aligning and feeding device capable of reliably aligning objects having a plane shape with an unequal ratio of length to width longitudinally and feeding them is provided.An aligning and feeding device has a rotary table 2 horizontally rotatable, drive means 3 for rotating the rotary table 2, a supply mechanism for supplying objects to be aligned onto the rotary table 2 and a guide mechanism 7 for defining a conveying path for the objects to be aligned conveyed by the rotary table 2. The guide mechanism 7 has an introduction guide 11, first pair of alignment guides 16, second pair of alignment guides 19 and pair of discharge guides 23 which each has a guide face and are disposed sequentially along the conveying path for the objects to be aligned. The first pair of alignment guides 16 and the second pair of alignment guides 19 each have an outer guide positioned so that a start point of its guide face is closer to the periphery of the rotary table 2 than an end point thereof, and an inner guide positioned so that a start point of its guide face is closer to the center of the rotary table 2 than an end point thereof.
摘要翻译：提供了一种能够可靠地对准具有长度与宽度不等比例的平面形状的物体并对其进行馈送的对准和进给装置。定位供料装置具有水平可旋转的旋转台2，用于旋转旋转工作台2的驱动装置3，用于供给对准于旋转工作台2的物体的供给机构和用于限定物体的输送路径的导向机构7 由旋转台2对准输送。引导机构7具有引导引导件11，第一对对齐引导件16，第二对对齐引导件19和一对排出引导件23，每个排出引导件23具有引导面并且沿着用于对准物体的输送路径。第一对对准引导件16和第二对准引导件19各自具有外引导件，其定位成使得其引导面的起点比其端点更靠近旋转台2的周边，并且内引导件定位成使得其引导面的起点比其端点更靠近旋转台2的中心。

3. 发明授权

US5364275A Memory card connector 失效
标题翻译：存储卡连接器
公开(公告)号：US5364275A
公开(公告)日：1994-11-15
申请号：US51856
申请日：1993-04-26
申请人： Yoshiyuki Ota , Masaki Sakaoka
发明人： Yoshiyuki Ota , Masaki Sakaoka
IPC分类号： G06K17/00 , G06K7/00 , H05K7/14 , H05K1/00
CPC分类号： G06K13/0806 , G06K7/0047
摘要： A memory card connector assembly superimposed on a substrate includes a plurality of memory card connectors stacked on top of each other whose contacts are to be connected to corresponding terminals of associated memory cards. The contacts of a lowermost memory card connector are soldered to the substrate, and the contacts of at least one upper memory card connector are connected to an FPC board.
摘要翻译：叠加在基板上的存储卡连接器组件包括堆叠在彼此顶部的多个存储卡连接器，其触点将连接到相关联的存储卡的相应端子。将最下面的存储卡连接器的触点焊接到基板上，并且至少一个上存储卡连接器的触点连接到FPC板。

4. 发明授权

US08175205B2 Clock data recovery circuit capable of generating clock signal synchronized with data signal 失效
标题翻译：时钟数据恢复电路能够产生与数据信号同步的时钟信号
公开(公告)号：US08175205B2
公开(公告)日：2012-05-08
申请号：US12883272
申请日：2010-09-16
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译：相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于一次等于输出时钟的一个周期的延迟与控制码相加或相减。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

5. 发明申请

US20110169401A1 PLASMA DISPLAY PANEL 审中-公开
标题翻译：等离子显示面板
公开(公告)号：US20110169401A1
公开(公告)日：2011-07-14
申请号：US12990363
申请日：2010-06-23
申请人： Shinsuke Yoshida , Akira Kawase , Kazuhiro Morioka , Naoto Haze , Yoshiyuki Ota , Morio Fujitani , Hiroshi Ito , Tatsuo Mifune
发明人： Shinsuke Yoshida , Akira Kawase , Kazuhiro Morioka , Naoto Haze , Yoshiyuki Ota , Morio Fujitani , Hiroshi Ito , Tatsuo Mifune
IPC分类号： H01J17/02
CPC分类号： H01J11/38 , H01J11/12
摘要： The PDP has front plate and a rear plate. Front plate and the rear plate are oppositely disposed and sealed at the peripheries. Front plate has display electrode and dielectric layer. Dielectric layer contains an oxide of a divalent element, an oxide of a trivalent element, and an oxide of a tetravalent element. The total content of the oxide of a trivalent element and the oxide of a tetravalent element is larger by weight than the content of the oxide of a divalent element.
摘要翻译： PDP具有前板和后板。前板和后板在周边相对设置和密封。前板具有显示电极和电介质层。介电层含有二价元素的氧化物，三价元素的氧化物和四价元素的氧化物。三价元素的氧化物和四价元素的氧化物的总含量比二价元素的氧化物的含量大。

6. 发明申请

US20070018704A1 Clock data recovery circuit capable of generating clock signal synchronized with data signal 失效
标题翻译：时钟数据恢复电路能够产生与数据信号同步的时钟信号
公开(公告)号：US20070018704A1
公开(公告)日：2007-01-25
申请号：US11477597
申请日：2006-06-30
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H03K5/01
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by PD, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译： PD检测VDL与DATA与VDL输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当根据PD的检测结果改变控制码时，当输出时钟与数据信号同步期间，当VDL的延迟量超过时钟的一个周期时，对应于等于一个周期的延迟的控制码的输出时钟被一次添加到/从控制码中减去。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

7. 发明申请

US20110007855A1 Clock Data Recovery Circuit Capable of Generating Clock Signal Synchronized with Data Signal 失效
标题翻译：能够产生与数据信号同步的时钟信号的时钟数据恢复电路
公开(公告)号：US20110007855A1
公开(公告)日：2011-01-13
申请号：US12883272
申请日：2010-09-16
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H04L7/04
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译：相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于一次等于输出时钟的一个周期的延迟与控制码相加或相减。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

8. 发明授权

US07822158B2 Clock data recovery circuit capable of generating clock signal synchronized with data signal 失效
标题翻译：时钟数据恢复电路能够产生与数据信号同步的时钟信号
公开(公告)号：US07822158B2
公开(公告)日：2010-10-26
申请号：US11477597
申请日：2006-06-30
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译：相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于一次等于输出时钟的一个周期的延迟与控制码相加或相减。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

9. 发明授权

US06617933B2 VCO circuit with wide output frequency range and PLL circuit with the VCO circuit 失效
标题翻译： VCO电路具有宽输出频率范围和PLL电路与VCO电路
公开(公告)号：US06617933B2
公开(公告)日：2003-09-09
申请号：US09884931
申请日：2001-06-21
申请人： Yoshiaki Ito , Yoshiyuki Ota
发明人： Yoshiaki Ito , Yoshiyuki Ota
IPC分类号： H03L700
CPC分类号： H03L7/0995 , H03L7/093
摘要： A voltage-controlled oscillating circuit according to the present invention includes: a bias voltage generating circuit outputting a bias voltage according to a control voltage; and a ring oscillator circuit receiving supply of the bias voltage to operate. The bias voltage generating circuit generates the bias voltage using a feedback circuit formed by an operational amplifier receiving supply of a power source voltage to operate. Therefore, an influence of a high frequency component overlapped on the power source voltage, that is an influence of noise, is suppressed, thereby enabling stable generation of an output clock having a small variation in phase.
摘要翻译：根据本发明的压控振荡电路包括：偏压生成电路，根据控制电压输出偏置电压; 以及环路振荡器电路，接收偏置电压的供给以进行操作。偏置电压产生电路使用由运算放大器形成的反馈电路产生偏置电压，该运算放大器接收电源电压的供电以进行操作。因此，抑制与电源电压重叠的高频分量的影响，即噪声的影响，从而能够稳定地产生相位变化小的输出时钟。

10. 发明授权

US06177827B1 Current mirror circuit and charge pump circuit 失效
标题翻译：电流镜电路和电荷泵电路
公开(公告)号：US06177827B1
公开(公告)日：2001-01-23
申请号：US09184649
申请日：1998-11-03
申请人： Yoshiyuki Ota
发明人： Yoshiyuki Ota
IPC分类号： G05F110
CPC分类号： G05F3/262
摘要： There is provided a current mirror circuit which suppresses variations in an output current resulting from the Early effect. A pair of transistors (T1, T2) of a conventional current mirror circuit have gates connected to each other, and sources connected to each other, with the gate and drain of one of the transistors short-circuited. The source and drain of the other transistor (T2) on an output current side are connected to the source and gate of a transistor (T3), respectively. The sources of all of the transistors (T1, T2, T3) are commonly connected to a constant current circuit comprised of a bias voltage generating circuit (VB1) and a transistor (T4). A bias point is determined so that the increase/decrease in a current (Iout) causes the increase/decrease in a current (Icom), and the sizes of the respective transistors are designed.
摘要翻译：提供了一种电流镜电路，其抑制由Early效应引起的输出电流的变化。常规电流镜电路的一对晶体管（T1，T2）具有彼此连接的栅极，并且彼此连接的源极与一个晶体管的栅极和漏极短路。输出电流侧的另一个晶体管（T2）的源极和漏极分别连接到晶体管（T3）的源极和栅极。所有晶体管（T1，T2，T3）的源极通常连接到由偏置电压产生电路（VB1）和晶体管（T4）构成的恒流电路。确定偏置点，使得电流（Iout）的增加/减小导致电流（Icom）的增加/减小，并且设计各个晶体管的尺寸。

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