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1. 发明授权

US4926175A Analog-digital converting circuit having high resolution and low power consumption 失效
标题翻译：模数转换电路具有高分辨率和低功耗
公开(公告)号：US4926175A
公开(公告)日：1990-05-15
申请号：US341563
申请日：1989-04-20
申请人： Yoshiro Ishizawa , Hiroshi Morito
发明人： Yoshiro Ishizawa , Hiroshi Morito
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/18
摘要： An analog-digital converting circuit comprises an analog amplifying circuit having different amplification factors and an input connected to an analog signal input terminal. A first selector is connected at a corresponding number of inputs to receive the plurality of amplified analog signals, respectively. The first selection circuit outputs one analog signal selected from the received amplified analog signals, to an analog-digital converter. A second selector is connected at its an input to receive a digital signal from the analog-digital converter and has a plurality of outputs for outputting the received digital signal from one sequentially alternatively selected from the plurality of outputs. A coefficient multiplying circuit is connected to the outputs of the second selector, and generates multiplied digital signals obtained by multiplying the outputs of the second selector by different coefficeints. A third selector is connected at its corresponding number of inputs to the plurality of outputs of the coefficient multiplying circuit so as to output, as a digital signal, one selected from the plurality of outputs of the coefficient multiplying circuit. A controller is connected to receive the plurality of outputs of the second selector for monitoring respective levels of the plurality of outputs of the second selector and for supplying a selection signal to the third selector so as to cause to select, from the plurality of outputs of the coefficient multiplying circuit, one multiplied digital signal in correspondence to a level of the analog signal inputted to the analog signal input terminal. y

2. 发明授权

US4589005A Charge transfer device having improved electrodes 失效
标题翻译：电荷转移装置具有改进的电极
公开(公告)号：US4589005A
公开(公告)日：1986-05-13
申请号：US500595
申请日：1983-06-02
申请人： Hajime Matsuda , Hiroshi Morito
发明人： Hajime Matsuda , Hiroshi Morito
IPC分类号： G11C27/04 , H01L21/339 , H01L29/423 , H01L29/76 , H01L29/762 , H01L29/768 , H01L29/772 , H01L29/78 , G11C19/28
CPC分类号： H01L29/768 , H01L29/42396 , H01L29/76
摘要： A charge transfer device in which a number of transfer electrodes, comprised of alternating main electrodes and auxiliary electrodes, are formed on but insulated from a channel region in a semiconductor substrate for transferring charges. The transfer electrodes are formed such that the sides of each of the electrodes which are transverse to the channel direction are concave in the direction of charge transfer. These concave sides produce an additional accelerating electric field which supplements the conventional fringing fields.
摘要翻译：一种电荷转移装置，其中由交替的主电极和辅助电极组成的多个转移电极形成在半导体衬底中，用于转移电荷但与沟道区绝缘。转印电极被形成为使得每个电极的横向于沟道方向的侧面在电荷转移方向上是凹的。这些凹面产生额外的加速电场，补充了传统的边缘场。

3. 发明授权

US5055917A Output apparatus for image signals 失效
标题翻译：用于图像信号的输出装置
公开(公告)号：US5055917A
公开(公告)日：1991-10-08
申请号：US350493
申请日：1989-05-11
申请人： Hidemitsu Nikoh , Hiroshi Morito
发明人： Hidemitsu Nikoh , Hiroshi Morito
IPC分类号： H04N9/64
CPC分类号： H04N9/64
摘要： An output apparatus for image signals includes an image signal processing circuit for providing a digital luminance signal, a digital color signal, a digital composite video signal etc., a multiplexing circuit for multiplexing these signals to be positioned alternately on a time axis, a D/A converter for converting the digital multiplexed signal to an analog multiplexed signal, and plural signal holding circuits for an analog luminance signal, an analog color signal, an analog composite video signal etc. separated from the analog multiplexed signal, respectively. Therefore, only one D/A converter is used therein, so that the cost is decreased and the size becomes small.

4. 发明授权

US5159614A Production of an address for effective use of a memory in a sound processing device 失效
标题翻译：生产有效使用声音处理设备中的存储器的地址
公开(公告)号：US5159614A
公开(公告)日：1992-10-27
申请号：US770231
申请日：1991-10-02
申请人： Hiroshi Morito
发明人： Hiroshi Morito
IPC分类号： G10L19/00 , G10K15/08 , G10K15/12 , G11C8/04
CPC分类号： G10K15/08 , G11C8/04
摘要： For one of memory divisions that is selected at a time as a selected division N(m) in a memory for use in putting a sound processing device in operation of generating a three-dimensional image of an acoustic field, a difference signal is produced to represent a clock count minus a delay count n(m) specific to the selected division and to have more and less significant bits. For use as an address signal supplied to the memory, a part of the more significant bits is changed to a like part of a memory space address specific to the selected division. As usual, the less significant bits are used to indicate read aR(i(m)) and write W(i(m)) pointers which are spaced in the selected division by the delay count. The part may be specified to be wide and narrow when the selected division is narrow and wide. Alternatively, the part may have a predetermined bit width.
摘要翻译：对于在用于将声音处理装置放置在产生声场的三维图像的操作中的存储器中作为所选择的分割N（m）在某一时刻被选择的存储器分割中的一个，产生差分信号，表示时钟计数减去特定于所选择的分频的延迟计数n（m），并具有越来越少的有效位。为了用作提供给存储器的地址信号，更高有效位的一部分被改变为特定于所选择的分区的存储器空间地址的相似部分。像往常一样，较低有效位用于指示读取aR（i（m））和写入W（i（m））指针，所述指针在所选择的除法中间隔延迟计数。当所选择的分割窄且宽时，该部分可以被指定为宽而窄。或者，该部分可以具有预定的位宽度。

5. 发明授权

US4694274A Data comparison circuit constructed with smaller number of transistors 失效
标题翻译：数据比较电路采用较少数量的晶体管构成
公开(公告)号：US4694274A
公开(公告)日：1987-09-15
申请号：US685149
申请日：1984-12-21
申请人： Jiroh Shimada , Hiroshi Morito
发明人： Jiroh Shimada , Hiroshi Morito
IPC分类号： G06F7/02 , H03K19/21 , G05B1/00 , G06F7/04
CPC分类号： H03K19/215 , G06F7/02
摘要： A circuit for comparing first and second binary coded digital data signals has a plurality of first circuits each including first and second transistors of a P-channel type connected in series between a first potential terminal and a first output node, a plurality of second circuits each including third and fourth transistors of an N-channel type connected in series between a second potential terminal and a second output node, and means for precharging the first and second output nodes to first and second logic levels, respectively. The first and third transistors are supplied with one bit data of the first signal, and the second and fourth transistors are supplied with an inverted data of the second signal. A change in the logic level at least one of the first and second output nodes is detected.
摘要翻译：用于比较第一和第二二进制编码数字数据信号的电路具有多个第一电路，每个第一电路包括串联连接在第一电位端子和第一输出节点之间的P沟道型的第一和第二晶体管，多个第二电路包括串联连接在第二电位端子和第二输出节点之间的N沟道型的第三和第四晶体管，以及用于分别将第一和第二输出节点预充电到第一和第二逻辑电平的装置。第一和第三晶体管被提供有第一信号的一位数据，第二和第四晶体管被提供有第二信号的反相数据。检测到第一和第二输出节点中的至少一个的逻辑电平的改变。

6. 发明授权

US06830195B2 Merchandise tag 失效
标题翻译：商品标签
公开(公告)号：US06830195B2
公开(公告)日：2004-12-14
申请号：US10395804
申请日：2003-03-24
申请人： Hiroshi Morito , Shunji Masuda
发明人： Hiroshi Morito , Shunji Masuda
IPC分类号： G06K1906
CPC分类号： G06K19/07758 , G06K19/07749 , G06K19/08
摘要： The disclosed merchandise tag is a non-contact wireless tag, has a color change layer on its surface, and the price data stored therein can be read out and rewritten. It can be easily attached and removed, reduces the amount of attachment implements used, and allows the display thereon to be easily changed by means of a heat treatment, magnetic treatment, or the like. The merchandise tag has an attachment hole 2 and a slit 3 that is formed to extend from the attachment hole up to the circumference of the merchandise tag, and contains a semiconductor integrated circuit, and one or more price data entries can be stored in the semiconductor integrated circuit. It preferably includes a rounded portion 4 at the intersection between the slit 3 and the circumference such that the angle formed between the slit 3 and the circumference is between 20 and 70 degrees.
摘要翻译：所公开的商品标签是非接触式无线标签，其表面上具有变色层，并且可以读出并重写其中存储的价格数据。可以容易地安装和拆卸，减少所使用的附着工具的数量，并且可以通过热处理，磁性处理等容易地改变其上的显示。商品标签具有附接孔2和狭缝3，该狭缝3形成为从附件孔延伸到商品标签的周边，并且包含半导体集成电路，并且一个或多个价格数据条目可以存储在半导体集成电路。它优选地包括在狭缝3和圆周之间的交叉处的圆形部分4，使得狭缝3和圆周之间形成的角度在20和70度之间。

7. 发明授权

US4591742A Output circuit capable of being connected to another circuit having transistors of any conduction type 失效
标题翻译：输出电路能够连接到具有任何导电类型的晶体管的另一个电路
公开(公告)号：US4591742A
公开(公告)日：1986-05-27
申请号：US492916
申请日：1983-05-09
申请人： Hiroshi Morito
发明人： Hiroshi Morito
IPC分类号： H03K5/02 , H03K19/018 , H03K19/0185 , H03K19/0952 , H03K19/21 , H03K17/687
CPC分类号： H03K19/215 , H03K19/018507 , H03K5/023 , H03K5/026
摘要： An integrated circuit having a signal terminal 13 and a reference terminal 14, an output transistor Q.sub.4 connected across these terminals with its gate or base connected to the output of exclusive OR gate 12, and an internal circuit 110 with its input port connected to the signal terminal and its output terminal connected to one of the inputs of the OR gate. The other OR-gate input is connected to the reference terminal. By applying the proper reference voltage to the reference terminal, the signal terminal can operate as an I/O terminal with another integrated circuit of the same or of different conductivity type.
摘要翻译：具有信号端子13和参考端子14的集成电路，连接在这些端子上的输出晶体管Q4，其栅极或基极连接到异或门12的输出，以及内部电路110，其输入端口连接到信号端子，其输出端子连接到OR门的一个输入端。另一个或门输入连接到参考端。通过将正确的参考电压施加到参考端子，信号端子可以作为具有相同或不同导电类型的另一个集成电路的I / O端子。

8. 发明授权

US4227214A Digital processing vertical synchronization system for a television receiver set 失效
标题翻译：电视接收机的数字处理垂直同步系统
公开(公告)号：US4227214A
公开(公告)日：1980-10-07
申请号：US924318
申请日：1978-07-13
申请人： Hiroshi Morito , Kenji Yamashita
发明人： Hiroshi Morito , Kenji Yamashita
IPC分类号： H04N5/06 , H04N5/12 , H04N5/04 , H04N5/10
CPC分类号： H04N5/12
摘要： A digital vertical synchronization system for use in a television receiver is disclosed. A vertical synchronization separator circuit receives a composite synchronizing signal and separates a vertical synchronizing signal from the composite signal. A clock counter receives a clock input signal having a frequency equal to a positive integer N times as high as the frequency of a horizontal synchronizing signal separated from the composite signal. The clock counter produces a first output signal having a repetition frequency substantially equal to the vertical synchronizing signal and having a pulse width required for generating a vertical deflection signal and a second output signal having a pulse width equal to or smaller than the pulse width of the vertical synchronizing signal. A phase comparator compares the phases of the second output signal of the clock counter and the vertical synchronizing signal and produces a reset signal when the phases of the two signals are not coincident. The reset signal is applied to the reset terminal of the clock counter.
摘要翻译：公开了一种用于电视接收机的数字垂直同步系统。垂直同步分离器电路接收复合同步信号，并从复合信号中分离垂直同步信号。时钟计数器接收具有等于从复合信号分离的水平同步信号的频率的N倍的正整数的频率的时钟输入信号。时钟计数器产生具有基本上等于垂直同步信号的重复频率并且具有产生垂直偏转信号所需的脉冲宽度的第一输出信号和具有等于或小于其的脉冲宽度的脉冲宽度的第二输出信号垂直同步信号。相位比较器比较时钟计数器的第二输出信号和垂直同步信号的相位，并且当两个信号的相位不一致时产生复位信号。复位信号被施加到时钟计数器的复位端。

9. 发明授权

US06762383B2 Sorting system 失效
标题翻译：排序系统
公开(公告)号：US06762383B2
公开(公告)日：2004-07-13
申请号：US10271520
申请日：2002-10-15
申请人： Hiroshi Morito
发明人： Hiroshi Morito
IPC分类号： B07C534
CPC分类号： B07C5/38
摘要： Articles entered into a sorting system are identified by means of an article identification device 1. An allocation ratio is selected from an allocation ratio table 7 based on the identifying information from the article identification device 1. Chute selection information is obtained for a sorter 2 based on the allocation ratio by means of a calculator 6, which in one embodiment uses a random number generator 8 to make a weighted calculation and a deviation reduction mechanism 11 to reduce the deviation of the accumulated weighted calculation results. A controller 3 selects a chute 4 such that the articles entered into the system will be distributed in accordance with the article allocation ratio, and provides the chute selection information to the sorter 2. The sorter 2, based upon the chute selection information, conducts sorting by dropping the articles entered into the system into the appropriate chute 4.
摘要翻译：通过物品识别装置1识别输入分拣系统的物品。基于来自物品识别装置1的识别信息，从分配比率表7中选择分配比率。基于分拣机2的滑槽选择信息通过计算器6，其在一个实施例中使用随机数发生器8进行加权计算，并且减少偏差减小机构11以减少积累的加权计算结果的偏差。控制器3选择滑槽4，使得输入到系统中的物品将根据物品分配比例分配，并将滑槽选择信息提供给分拣机2.分拣机2基于滑槽选择信息进行排序将进入系统的物品放入适当的滑槽4中。

10. 发明授权

US4573178A Counter employing feedback shift register controlling hysteresis circuit 失效
标题翻译：计数器采用反馈移位寄存器控制迟滞电路
公开(公告)号：US4573178A
公开(公告)日：1986-02-25
申请号：US756566
申请日：1985-07-18
申请人： Hiroshi Morito
发明人： Hiroshi Morito
IPC分类号： H03K27/00 , H03K3/2893 , H03K3/3565 , H03K3/84 , H03K23/54 , H03K25/12
CPC分类号： H03K3/3565 , H03K23/54 , H03K3/2893 , H03K3/84
摘要： A counter for counting pulses or dividing frequencies has a timing signal generator circuit for generating a timing signal at a predetermined interval. A hysteresis circuit has input-output characteristics defining a low input threshold level and a high input threshold level. A control circuit responds to the timing signal for generating at least three control signals having different levels including a first control signal having a level lower than the low input threshold level, a second control signal having a level higher than the high input threshold level, and a third control signal having an intermediate level which is between the low input threshold level and the high input threshold level. The counter has a very large capacity, simple construction, and is effective with both analog and digital signals.
摘要翻译：用于计数脉冲或分频的计数器具有用于以预定间隔产生定时信号的定时信号发生器电路。滞后电路具有定义低输入阈值电平和高输入阈值电平的输入 - 输出特性。控制电路响应于定时信号，用于产生具有不同电平的至少三个控制信号，包括具有低于低输入阈值电平的电平的第一控制信号，具有高于高输入阈值电平的电平的第二控制信号，以及具有处于低输入阈值电平和高输入阈值电平之间的中间电平的第三控制信号。该计数器具有非常大的容量，结构简单，并且对模拟和数字信号都有效。

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