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1. 发明授权

US08067101B2 Capacitor electrode and method of manufacturing the same 有权
标题翻译：电容器电极及其制造方法
公开(公告)号：US08067101B2
公开(公告)日：2011-11-29
申请号：US12441681
申请日：2007-09-14
申请人： Yoshiko Hishitani , Hidetoshi Nojiri , Didier Hamm , Masaharu Hatano , Makoto Uchiyama
发明人： Yoshiko Hishitani , Hidetoshi Nojiri , Didier Hamm , Masaharu Hatano , Makoto Uchiyama
IPC分类号： H01G4/228 , H01G9/00 , B05D3/00 , G11B11/105 , B32B9/00 , B32B19/00
CPC分类号： H01G9/058 , H01G9/22 , H01G11/02 , H01G11/46 , H01G11/84 , Y02E60/13 , Y10T29/43 , Y10T428/26
摘要： This invention relates to a capacitor electrode which includes porous layers made of a fiber and/or a whisker containing crystal tungsten oxides. The tungsten oxide fiber and/or whisker contain W18O49 as a main ingredient. The tungsten oxide fiber and/or whisker are made on a substrate. When manufacturing the capacitor electrode the substrate or its precursor is heated in vacuo or in an inactive containing a minute amount of oxygen, thereby completing the fiber and/or whisker.
摘要翻译：本发明涉及一种电容器电极，其包括由含有晶体氧化钨的纤维和/或晶须制成的多孔层。氧化钨纤维和/或晶须含有W18O49作为主要成分。氧化钨纤维和/或晶须在基材上制成。当制造电容器电极时，将衬底或其前体在真空中或在含有少量氧气的无活性物质中加热，由此完成纤维和/或晶须。

2. 发明申请

US20090268371A1 CAPACITOR ELECTRODE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：电容器电极及其制造方法
公开(公告)号：US20090268371A1
公开(公告)日：2009-10-29
申请号：US12441681
申请日：2007-09-14
申请人： Yoshiko Hishitani , Hidetoshi Nojiri , Didier Hamm , Masaharu Hatano , Makoto Uchiyama
发明人： Yoshiko Hishitani , Hidetoshi Nojiri , Didier Hamm , Masaharu Hatano , Makoto Uchiyama
IPC分类号： H01G4/008 , H01G4/005
CPC分类号： H01G9/058 , H01G9/22 , H01G11/02 , H01G11/46 , H01G11/84 , Y02E60/13 , Y10T29/43 , Y10T428/26
摘要： This invention relates to a capacitor electrode which includes porous layers made of a fiber and/or a whisker containing crystal tungsten oxides. The tungsten oxide fiber and/or whisker contain W18O49 as a main ingredient. The tungsten oxide fiber and/or whisker are made on a substrate. When manufacturing the capacitor electrode the substrate or its precursor is heated in vacuo or in an inactive containing a minute amount of oxygen, thereby completing the fiber and/or whisker.
摘要翻译：本发明涉及一种电容器电极，其包括由含有晶体氧化钨的纤维和/或晶须制成的多孔层。氧化钨纤维和/或晶须含有W18O49作为主要成分。氧化钨纤维和/或晶须在基材上制成。当制造电容器电极时，将衬底或其前体在真空中或在含有少量氧气的无活性物质中加热，由此完成纤维和/或晶须。

3. 发明申请

US20060196410A1 Whisker-grown body and electrochemical capacitor using the same 审中-公开
标题翻译：晶须生长体和电化学电容器使用相同
公开(公告)号：US20060196410A1
公开(公告)日：2006-09-07
申请号：US11354242
申请日：2006-02-15
申请人： Yoshiko Hishitani , Makoto Uchiyama , Hidetoshi Nojiri
发明人： Yoshiko Hishitani , Makoto Uchiyama , Hidetoshi Nojiri
IPC分类号： C30B9/00 , C30B11/00 , C30B17/00 , C30B21/02 , C30B28/06
CPC分类号： H01G9/058 , C30B1/00 , C30B29/16 , C30B29/62 , H01G9/016 , H01G11/24 , H01G11/26 , Y02E60/13
摘要： A whisker-grown body of the present invention includes a raw material substrate made of manganese-containing metal and/or ceramics, and a whisker containing 50% by mass or more of manganese dioxide and formed on a surface of the raw material substrate. The whisker-grown body has a high surface ratio to unit volume and improves electrode efficiency when used as an electrode of an electrochemical capacitor.
摘要翻译：本发明的晶须生长体包括由含锰金属和/或陶瓷制成的原料基材和在原料基材的表面上形成的含有50质量％以上的二氧化锰的晶须。晶须生长体与单位体积具有高的表面比，并且当用作电化学电容器的电极时提高电极效率。

4. 发明授权

US07074513B2 Unit cell for solid electrolyte type fuel cell and related manufacturing method 失效
公开(公告)号：US07074513B2
公开(公告)日：2006-07-11
申请号：US10302856
申请日：2002-11-25
申请人： Itaru Shibata , Masaharu Hatano , Tatsuhiro Fukuzawa , Naoki Hara , Dong Song , Yoshiko Hishitani , Fuminori Satou , Keiko Kushibiki , Makoto Uchiyama , Mitsugu Yamanaka
发明人： Itaru Shibata , Masaharu Hatano , Tatsuhiro Fukuzawa , Naoki Hara , Dong Song , Yoshiko Hishitani , Fuminori Satou , Keiko Kushibiki , Makoto Uchiyama , Mitsugu Yamanaka
IPC分类号： H01M8/04 , H01M8/12 , H01M4/86
CPC分类号： H01M8/12 , H01M8/0202 , Y02P70/56
摘要： A unit cell for a solid electrolyte type fuel cell is provided with a fuel electrode, an air electrode making a pair with the fuel electrode, a solid electrolyte interposed between the fuel electrode and the air electrode, a porous metallic base body disposed on at lease one of a surface of the fuel electrode on the far side from the solid electrolyte and a surface of the air electrode on the far side from the solid electrolyte such that the fuel electrode, the electrolyte, and a plurality of concave portions formed in the porous metallic base body so as to extend, in a laminating direction in which the fuel electrode, the electrolyte, the air electrode and the porous metallic base body are laminated, from a surface of the porous metallic base body.

5. 发明授权

US07157169B2 Fuel cell 有权
标题翻译：燃料电池
公开(公告)号：US07157169B2
公开(公告)日：2007-01-02
申请号：US10274880
申请日：2002-10-22
申请人： Keiko Kushibiki , Masaharu Hatano , Itaru Shibata , Tatsuhiro Fukuzawa , Naoki Hara , Dong Song , Yoshiko Hishitani , Fuminori Satou , Makoto Uchiyama , Mitsugu Yamanaka
发明人： Keiko Kushibiki , Masaharu Hatano , Itaru Shibata , Tatsuhiro Fukuzawa , Naoki Hara , Dong Song , Yoshiko Hishitani , Fuminori Satou , Makoto Uchiyama , Mitsugu Yamanaka
IPC分类号： H01M8/04
CPC分类号： H01M8/0267 , H01M8/0297 , H01M8/04022 , H01M8/2425 , H01M8/243 , H01M8/2465
摘要： A fuel cell of the present invention includes a fuel cell stack (1) for being formed by stacking a plurality of cell plates (2) having a flat shape, the cell plates (2) being configured by arranging a plurality of cells, the cell having an electrolyte layer (2a), a fuel electrode layer (2b) and an air electrode layer (2c). A combustion heater plate (3) includes a porous combustion plate (3a) and a gas non-pass layer (3b) covering a surface of the porous combustion plate (3a). The combustion heater plate (3) is disposed between the cell plates (2).
摘要翻译：本发明的燃料电池包括通过堆叠多个具有扁平形状的电池板（2）形成的燃料电池组（1），电池板（2）通过布置多个电池而构成，电池单元具有电解质层（2a），燃料电极层（2b）和空气电极层（2c）。燃烧加热器板（3）包括多孔燃烧板（3a）和覆盖多孔燃烧板（3a）的表面的气体非通过层（3b）。燃烧加热器板（3）设置在电池板（2）之间。

6. 发明授权

US5173149A Method of etching semiconductor substrate 失效
标题翻译：蚀刻半导体衬底的方法
公开(公告)号：US5173149A
公开(公告)日：1992-12-22
申请号：US665546
申请日：1991-03-07
申请人： Hidetoshi Nojiri , Makoto Uchiyama
发明人： Hidetoshi Nojiri , Makoto Uchiyama
IPC分类号： H01L21/306 , H01L21/3063
CPC分类号： H01L21/3063
摘要： To eliminate the influence of fluctuations in etching liquid sorts, composition, density, degradation, temperature, agitation etc., a method of selectively etching a semiconductor substrate having an n-type layer and a p-type layer and immersed in an electrolytic solution comprises the steps of: applying an etching voltage to the n-type layer; integrating etching current flowing through the substrate; if the integrated current value exceeds a reference value required to etch the p-type layer to a predetermined depth, increasing the etching voltage; if the potential of the substrate relative to a reference electrode reaches a predetermined value at which only the p-type layer can be etched, keeping the increased etching voltage at the current level to further etch only the p-type layer; and if the etching current drops sharply due to formation of an anodic oxidation film on the n-type layer, completing the substrate etching.
摘要翻译：为了消除蚀刻液体种类，组成，密度，降解，温度，搅拌等的波动的影响，选择性地蚀刻具有n型层和p型层并浸没在电解液中的半导体衬底的方法包括步骤：向n型层施加蚀刻电压; 积分流过衬底的蚀刻电流; 如果积分电流值超过将p型层蚀刻到预定深度所需的参考值，则增加蚀刻电压; 如果衬底相对于参考电极的电位达到只能蚀刻p型层的预定值，则将增加的蚀刻电压保持在当前电平以仅进一步蚀刻p型层; 并且如果蚀刻电流由于在n型层上形成阳极氧化膜而急剧下降，则完成基板蚀刻。

7. 发明授权

US4962062A Method of tightly joining two semiconductor substrates 失效
标题翻译：紧密接合两个半导体衬底的方法
公开(公告)号：US4962062A
公开(公告)日：1990-10-09
申请号：US238421
申请日：1988-08-31
申请人： Makoto Uchiyama , Hidetoshi Nojiri
发明人： Makoto Uchiyama , Hidetoshi Nojiri
IPC分类号： H01L21/02 , H01L21/18
CPC分类号： H01L21/187 , Y10S148/012 , Y10S148/135
摘要： Two semiconductor substrates, each having a polished surface and at least one groove is formed in the surface of at least one of the two substrates, are tightly and inseparably joined by the steps of wetting the polished surface of at least one of the two substrates with a liquid not containing any solute that causes precipitation of a solid substance upon evaporation of the liquid, e.g. methanol or water, placing one substrate on the other so as to bring the polished surfaces of the two substrates into contact with each other with intervention of a thin film of the liquid therebetween and, after a while, subjecting the provisionally joined substrates to a heat treatment and then forming a dielectric layer of organic polymer or silicon compound in at least one groove. This method is suitable for joining silicon substrates such as silicon wafers now on the market. The two semiconductor substrates may be different in the type of conductivity or in the concentration of impurity, and at least one of the two substrates may have a diffused layer, a dielectric layer of a polycrystalline layer as a surface layer having the polished surface.
摘要翻译：在两个基板中的至少一个基板的表面上形成两个具有抛光表面和至少一个凹槽的半导体基板，通过以下步骤紧密地和不可分离地连接，所述步骤是通过以下步骤将两个基板中的至少一个的抛光表面润湿，不含任何溶质的液体，其在液体蒸发时引起固体物质的沉淀，例如，甲醇或水，将一个基板放置在另一个上，以使两个基板的抛光表面彼此接触，同时介入其间的液体薄膜，并且在一段时间之后，使临时接合的基板经受热处理，然后在至少一个凹槽中形成有机聚合物或硅化合物的介电层。该方法适用于现在市场上连接诸如硅晶片的硅衬底。两个半导体衬底的导电类型或杂质浓度可以不同，并且两个衬底中的至少一个可以具有扩散层，作为具有抛光表面的表面层的多晶层的电介质层。

8. 发明授权

US5681448A Electrochemical process and system for etching semiconductor substrates 失效
标题翻译：用于蚀刻半导体衬底的电化学工艺和系统
公开(公告)号：US5681448A
公开(公告)日：1997-10-28
申请号：US578920
申请日：1995-12-27
申请人： Makoto Uchiyama , Hidetoshi Nojiri , Yasukazu Iwasaki
发明人： Makoto Uchiyama , Hidetoshi Nojiri , Yasukazu Iwasaki
IPC分类号： C25F3/12 , C25F7/00
CPC分类号： C25F3/12 , C25F7/00
摘要： An electrochemical etching process carried out in an etching system including an electrolysis vessel which is provided thereinside with facing wall surfaces defining therebetween an etching solution flow region. A semiconductor substrate to be etched and a counter electrode are mounted respectively on the facing wall surfaces. A flow stream generating section for the etching solution is formed separate from the etching solution flow region and includes a device for generating the flow stream of the etching solution. The flow stream generating section is connected to the etching solution flow region in such a manner that the etching solution flow in a direction generally parallel with the facing wall surfaces inside the electrolysis vessel. An electric potential is applied between the semiconductor substrate and the counter electrode to accomplish an electrochemical etching on the semiconductor substrate.
摘要翻译：在包括电解容器的蚀刻系统中执行的电化学蚀刻工艺，其中设置有电解槽，其中在其间限定有蚀刻溶液流动区域。要蚀刻的半导体衬底和对电极分别安装在相对的壁表面上。用于蚀刻溶液的流动流产生部分与蚀刻溶液流动区域分离形成，并且包括用于产生蚀刻溶液的流动流的装置。流动流产生部分以蚀刻溶液流动方向大致平行于电解容器内的相对的壁表面的方式连接到蚀刻液流动区域。在半导体衬底和对电极之间施加电位以在半导体衬底上实现电化学蚀刻。

9. 发明授权

US5172207A Semiconductor wafer to be etched electrochemically 失效
标题翻译：要电化学蚀刻的半导体晶片
公开(公告)号：US5172207A
公开(公告)日：1992-12-15
申请号：US747582
申请日：1991-08-20
申请人： Hidetoshi Nojiri , Makoto Uchiyama
发明人： Hidetoshi Nojiri , Makoto Uchiyama
IPC分类号： C25F3/30 , H01L21/306 , H01L21/3063
CPC分类号： H01L21/3063
摘要： A semiconductor wafer including a plurality of chips having respective portions to be etched electrochemically with application of an electric voltage to the semiconductor wafer immersed in an etching solution. The semiconductor wafer includes electric circuits formed therein for controlling electric energy applied to the respective portions.
摘要翻译：一种半导体晶片，其包括多个芯片，其具有将要浸入蚀刻溶液中的半导体晶片施加电压的电化学蚀刻的各部分。半导体晶片包括形成在其中的用于控制施加到各个部分的电能的电路。

10. 发明授权

US5167778A Electrochemical etching method 失效
标题翻译：电化学蚀刻法
公开(公告)号：US5167778A
公开(公告)日：1992-12-01
申请号：US740521
申请日：1991-08-05
申请人： Hiroyuki Kaneko , Makoto Uchiyama , Hidetoshi Nojiri , Norihiko Kiritani
发明人： Hiroyuki Kaneko , Makoto Uchiyama , Hidetoshi Nojiri , Norihiko Kiritani
IPC分类号： G01L9/04 , C25F3/30 , G01L9/00 , H01L21/3063 , H01L29/84
CPC分类号： H01L21/3063
摘要： An electrochemical etching method for producing semiconductor diaphragms from a semiconductor wafer comprised of a first semiconductor layer of a first conductivity type and a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a second conductivity type different than the first semiconductor layer. The semiconductor wafer is placed in an etching solution with respect to a counter-electrode immersed in the etching solution. The semiconductor wafer has a plurality of chips each of which includes at least one third semiconductor layer of the first conductivity type. The third semiconductor layer extends through the second semiconductor layer to the first semiconductor layer. A first positive potential is applied to the first and third semiconductor layers with respect to the counter-electrode. A second positive potential is applied to the second semiconductor layer with respect to the first semiconductor layer.
摘要翻译：一种用于从由第一导电类型的第一半导体层和形成在第一半导体层上形成的第二半导体层的半导体晶片制造半导体膜片的电化学蚀刻方法，所述第二半导体层具有不同于第一半导体层的第二导电类型。将半导体晶片相对于浸在蚀刻溶液中的对电极放置在蚀刻溶液中。半导体晶片具有多个芯片，每个芯片包括至少一个第一导电类型的第三半导体层。第三半导体层延伸穿过第二半导体层到第一半导体层。第一和第三半导体层相对于反电极施加第一正电位。第二正电位相对于第一半导体层施加到第二半导体层。

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