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    • 4. 发明授权
    • DRAM having test circuit capable of performing function test of refresh
counter and measurement of refresh cycle simultaneously
    • DRAM具有能够同时进行刷新计数器的功能测试和刷新周期的测量的测试电路
    • US5625597A
    • 1997-04-29
    • US627126
    • 1996-04-03
    • Yoshihiko Hirose
    • Yoshihiko Hirose
    • G11C11/406G11C11/401G11C11/403G11C11/409G11C29/00G11C29/02G11C29/08G11C29/50
    • G11C29/02
    • According to the present invention, there is provided a circuit structure capable of carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation. The counter generates a refresh row address. The bit line sense amplifier circuit connected to a bit line pair for transmitting data of a memory cell, consists of the N-channel sense amplifier and the P-channel sense amplifier. The sense amplifier driving circuit supplies respective driving signals for the N-channel sense amplifier and the P-channel sense amplifier. The test control circuit is provided for carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation, and controls the driving signals so as to set one of the N-channel sense amplifier and the P-channel sense amplifier in a non-active state at the time of a test mode.
    • 根据本发明,提供了一种电路结构,其能够执行刷新计数器的功能测试和刷新操作时的计数器周期的测量。 计数器生成刷新行地址。 连接到用于发送存储单元的数据的位线对的位线读出放大器电路由N沟道读出放大器和P沟道读出放大器组成。 读出放大器驱动电路为N沟道读出放大器和P沟道读出放大器提供相应的驱动信号。 测试控制电路用于在刷新操作时执行刷新计数器的功能测试和计数器周期的测量,并且控制驱动信号以便设置N沟道读出放大器和 在测试模式时处于非活动状态的P通道读出放大器。