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1. 发明申请

US20080102639A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH RECESS GATE 失效
标题翻译：用于制造具有压盖的半导体器件的方法
公开(公告)号：US20080102639A1
公开(公告)日：2008-05-01
申请号：US11928056
申请日：2007-10-30
申请人： Yong-Tae CHO , Suk-Ki KIM , Sang-Hoon CHO
发明人： Yong-Tae CHO , Suk-Ki KIM , Sang-Hoon CHO
IPC分类号： H01L21/467
CPC分类号： H01L29/66621 , H01L21/3065 , H01L21/3083 , H01L21/3086
摘要： A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.
摘要翻译：一种用于制造半导体器件的方法包括：在衬底上形成硬掩模图案，在衬底中形成第一凹槽，并使用硬掩模图案作为蚀刻阻挡层，在第一凹槽的侧壁上形成钝化层，并形成第二凹槽使用钝化层蚀刻第一凹部的底部作为蚀刻阻挡层，其中第二凹部的宽度大于第一凹部的宽度。

2. 发明申请

US20080113500A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING RECESS GATE 有权
标题翻译：用于制造包括收缩门的半导体器件的方法
公开(公告)号：US20080113500A1
公开(公告)日：2008-05-15
申请号：US11768620
申请日：2007-06-26
申请人： Suk-Ki KIM , Yong-Tae CHO
发明人： Suk-Ki KIM , Yong-Tae CHO
IPC分类号： H01L21/4763
CPC分类号： H01L29/66621 , H01L21/28061
摘要： A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate having a field oxide layer, etching the substrate to form a recess by using the hard mask pattern, forming a first conductive layer over the recess and the hard mask pattern, planarizing the first conductive layer, and forming a second conductive layer over the planarized first conductive layer.
摘要翻译：一种制造半导体器件的方法包括在具有场氧化物层的衬底上形成硬掩模图案，通过使用硬掩模图案蚀刻衬底以形成凹部，在凹部上形成第一导电层和硬掩模图案，平面化第一导电层，以及在平坦化的第一导电层上形成第二导电层。

3. 发明申请

US20110266634A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110266634A1
公开(公告)日：2011-11-03
申请号：US13184272
申请日：2011-07-15
申请人： Yong-Tae CHO , Hae-Jung LEE , Eun-Mi KIM , Kyeong-Hyo LEE
发明人： Yong-Tae CHO , Hae-Jung LEE , Eun-Mi KIM , Kyeong-Hyo LEE
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/7851
摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.
摘要翻译：在制造半导体器件及其相关方法中，在衬底上形成硬掩模层，硬掩模层和衬底的部分被蚀刻以形成在侧壁具有突出部分的沟槽，并且埋在沟槽中的绝缘层被形成以形成在侧壁具有突出部分的器件隔离区域，其中器件隔离区域减小有效区域宽度的一部分。

4. 发明申请

US20110266648A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
公开(公告)号：US20110266648A1
公开(公告)日：2011-11-03
申请号：US13184235
申请日：2011-07-15
申请人： Yong-Tae CHO , Hae-Jung LEE , Eun-Mi KIM , Kyeong-Hyo LEE
发明人： Yong-Tae CHO , Hae-Jung LEE , Eun-Mi KIM , Kyeong-Hyo LEE
IPC分类号： H01L27/10
CPC分类号： H01L29/66795 , H01L29/7851
摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

5. 发明申请

US20080160742A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH RECESS GATE 审中-公开
标题翻译：用于制造具有压盖的半导体器件的方法
公开(公告)号：US20080160742A1
公开(公告)日：2008-07-03
申请号：US11963989
申请日：2007-12-24
申请人： Yong-Tae CHO , Hae-Jung LEE
发明人： Yong-Tae CHO , Hae-Jung LEE
IPC分类号： H01L21/3205
CPC分类号： H01L29/66621 , H01L29/1037 , H01L29/42376 , H01L29/66553
摘要： A method for fabricating a semiconductor device having a recess gate includes forming a first recess pattern by etching the substrate and a sidewall protection layer on sidewalls of the first recess pattern, forming a second recess pattern having a greater width than the first recess pattern by etching a certain portion of the substrate below a bottom portion of the first recess pattern, and forming a gate electrode filling the first and the second recess patterns.
摘要翻译：一种制造具有凹陷栅的半导体器件的方法包括：通过在第一凹槽图案的侧壁上蚀刻衬底和侧壁保护层来形成第一凹槽图案，通过蚀刻形成宽度大于第一凹槽图案的第二凹槽图案所述基板的位于所述第一凹部图案的底部下方的一部分，以及形成填充所述第一凹部图案和所述第二凹部图案的栅电极。

6. 发明申请

US20090130841A1 METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成接触的方法
公开(公告)号：US20090130841A1
公开(公告)日：2009-05-21
申请号：US12163434
申请日：2008-06-27
申请人： Yong-Tae CHO , Jae-Kyun LEE , Sang- Rok OH
发明人： Yong-Tae CHO , Jae-Kyun LEE , Sang- Rok OH
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76844
摘要： A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask.
摘要翻译：一种用于在半导体器件中形成接触的方法，包括提供衬底，在衬底上形成多个导电图案和围绕导电图案的钝化层，形成覆盖导电图案和钝化层的绝缘层，形成掩模图案对于绝缘层上的接触，通过使用掩模图案作为蚀刻掩模对绝缘层进行各向同性蚀刻工艺形成第一开口，其中执行各向同性蚀刻工艺，直到绝缘层与钝化层相交，形成屏障在所述第一开口的结果结构上方，通过使用所述掩模图案作为蚀刻掩模执行各向异性蚀刻工艺来暴露所述绝缘层，以及通过使用所述掩模通过执行自对准接触（SAC）工艺来形成第二开口，所述第二开口暴露所述衬底图案和阻挡层作为蚀刻掩模。

7. 发明申请

US20090087960A1 METHOD FOR FABRICATING RECESS GATE IN SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件中制造记忆门的方法
公开(公告)号：US20090087960A1
公开(公告)日：2009-04-02
申请号：US12239492
申请日：2008-09-26
申请人： Yong-Tae CHO , Eun-Mi Kim
发明人： Yong-Tae CHO , Eun-Mi Kim
IPC分类号： H01L21/76 , H01L21/302
CPC分类号： H01L21/28114 , H01L29/4236 , H01L29/42372 , H01L29/66621
摘要： A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.
摘要翻译：一种在半导体器件中制造凹陷栅的方法，包括蚀刻硅衬底以形成限定有源区的沟槽，形成间隙填充沟槽的器件隔离层，在硅衬底上形成硬掩模层，硬的掩模层，其包括氧化物层和非晶碳层的堆叠，其中所述硬掩模层暴露所述有源区的沟道目标区域，并且通过第一蚀刻形成具有双轮廓的凹陷区域，并且使用所述硬掩模层作为蚀刻阻挡层，其中所述第二蚀刻在去除所述无定形碳层之后进行。

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