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1. 发明申请

US20110233506A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110233506A1
公开(公告)日：2011-09-29
申请号：US12873604
申请日：2010-09-01
申请人： Yoko IWAKAJI , Jun HIROTA , Moto YABUKI
发明人： Yoko IWAKAJI , Jun HIROTA , Moto YABUKI
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： G11C13/0002 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L29/868 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a resistance change portion and a select element. The resistance change portion is provided between the first electrode and the second electrode and configured to transition between a first resistance state and a second resistance state. The select element is provided between the resistance change portion and the first electrode and has a p-layer including a p-type semiconductor, an i-layer including an intrinsic semiconductor, and an n-layer including an n-type semiconductor. The select element contains an impurity having a smaller bandgap energy than the intrinsic semiconductor, and a concentration peak of the impurity in the i-layer is placed in a center portion of layer thickness of the i-layer.
摘要翻译：根据一个实施例，非易失性存储器件包括第一电极，第二电极，电阻变化部分和选择元件。电阻变化部分设置在第一电极和第二电极之间并且被配置为在第一电阻状态和第二电阻状态之间转变。选择元件设置在电阻变化部分和第一电极之间，并且具有包括p型半导体的p层，包括本征半导体的i层和包括n型半导体的n层。选择元件含有具有比本征半导体更小的带隙能量的杂质，并且将i层中的杂质的浓度峰值放置在i层的层厚度的中心部分。

2. 发明申请

US20110227025A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110227025A1
公开(公告)日：2011-09-22
申请号：US12872284
申请日：2010-08-31
申请人： Jun HIROTA , Yoko Iwakaji , Moto Yabuki
发明人： Jun HIROTA , Yoko Iwakaji , Moto Yabuki
IPC分类号： H01L45/00 , H01L29/868 , H01L21/77
CPC分类号： H01L27/1021 , H01L27/101
摘要： According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.
摘要翻译：根据一个实施例，半导体存储器件包括字线互连层，位线互连层和柱。字线互连层包括沿第一方向延伸的多个字线。位线互连层包括沿与第一方向交叉的第二方向延伸的多个位线。支柱布置在每个字线和每个位线之间。支柱包括硅二极管和可变电阻膜，并且硅二极管包括p型部分和n型部分。字线互连层和位线互连层交替堆叠，并且在p型部分和n型部分变得更接近的方向上对硅二极管施加压缩力。

3. 发明申请

US20080296769A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080296769A1
公开(公告)日：2008-12-04
申请号：US12126284
申请日：2008-05-23
申请人： Jun HIROTA
发明人： Jun HIROTA
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/76802 , H01L21/76846 , H01L21/76849 , H01L21/76856 , H01L21/76865 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an embodiment of the present invention includes a line layer containing Cu (copper), an inter layer dielectric formed on the line layer, a via hole formed in the inter layer dielectric on the line layer, a first barrier layer formed on the line layer in the via hole, a second barrier layer formed on the first barrier layer and on a sidewall of the via hole, and a conductive layer formed on the second barrier layer and containing Al (aluminum).
摘要翻译：根据本发明的实施例的半导体器件包括：包含Cu（铜）的线层，在线层上形成的层间电介质，形成在线层上的层间电介质中的通孔，形成的第一阻挡层在通孔的线层上，形成在第一阻挡层上和通孔的侧壁上的第二阻挡层和形成在第二阻挡层上并含有Al（铝）的导电层。

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