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1. 发明授权

US06986072B2 Register capable of corresponding to wide frequency band and signal generating method using the same 有权
公开(公告)号：US06986072B2
公开(公告)日：2006-01-10
申请号：US10206822
申请日：2002-07-29
申请人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： G11C7/08 , G06F1/06 , G06F1/10
CPC分类号： G11C5/04 , G11C5/00 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/222 , H03L7/0814
摘要： A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

2. 发明授权

US06707726B2 Register without restriction of number of mounted memory devices and memory module having the same 有权
标题翻译：在不限制安装的存储器件的数量和具有相同的存储器模块的情况下进行注册
公开(公告)号：US06707726B2
公开(公告)日：2004-03-16
申请号：US10206823
申请日：2002-07-29
申请人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C2207/107
摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.
摘要翻译：第一和第二预处理触发器通过具有外部时钟信号的1/2的频率的时钟及其反时钟来锁存输入到寄存器的命令/地址信号。因此，命令/地址信号被分解成一组暂时具有两次的信号。例如，该组信号之一仅具有奇数命令/地址信号的数据内容，而另一个仅具有偶数个命令/地址信号的数据内容。由于该组信号具有两个命令/地址信号的周期，所以第一和第二后处理触发器可以根据由延迟锁定环电路产生的内部时钟信号来锁存信号，时间和保持时间充分确保。

3. 发明授权

US07411806B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07411806B2
公开(公告)日：2008-08-12
申请号：US11634405
申请日：2006-12-06
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

4. 发明授权

US07161820B2 Memory module and memory system having an expandable signal transmission, increased signal transmission and/or high capacity memory 有权
标题翻译：具有可扩展信号传输，增加的信号传输和/或高容量存储器的存储器模块和存储器系统
公开(公告)号：US07161820B2
公开(公告)日：2007-01-09
申请号：US10628517
申请日：2003-07-28
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/00 , G11C5/06
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

5. 发明授权

US07051225B2 Memory system, module and register 有权
标题翻译：内存系统，模块和寄存器
公开(公告)号：US07051225B2
公开(公告)日：2006-05-23
申请号：US10427090
申请日：2003-04-30
申请人： Yoji Nishio , Kayoko Shibata , Seiji Funaba
发明人： Yoji Nishio , Kayoko Shibata , Seiji Funaba
IPC分类号： G06F1/04
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1093
摘要： Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register. Alternatively, control is made for switching between the replica (replical) provided in the register and an output unit associated with the replica, depending on the frequency being used, so as to cope with both frequencies simply by providing one sort of the module and one sort of the register.
摘要翻译：公开了一种存储器命令地址系统和存储器模块，其不仅可以用于266MHzCLK，而且可以用于200MHzCLK，其中PLL，寄存器和DRAM的输入部分中的时钟定时彼此匹配，在寄存器中提供DLL（延迟锁定环），控制来自寄存器的CA信号的输出定时，使得CA信号的建立时间余量和保持时间裕度相对于时钟信号具有额外的等待时间 DRAM = 1.5或2.0彼此相等，使得例如266MHz的时钟操作成为可能。如果使用266MHz和200MHz，通过考虑时序预算，进行控制以延迟输入到触发器的CA信号的定时，该触发器接收提供给触发器的内部时钟信号（intCLK）用于确定来自寄存器的CA信号输出定时。或者，根据所使用的频率，进行控制以在寄存器中提供的副本（复制）和与副本相关联的输出单元之间进行切换，从而简单地通过提供一种模块和一个模块来处理两个频率排序的注册表。

6. 发明申请

US20070081376A1 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US20070081376A1
公开(公告)日：2007-04-12
申请号：US11634405
申请日：2006-12-06
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

7. 发明授权

US07016212B2 Memory module and memory system suitable for high speed operation 失效
标题翻译：内存模块和内存系统适合高速运行
公开(公告)号：US07016212B2
公开(公告)日：2006-03-21
申请号：US10630457
申请日：2003-07-29
申请人： Kayoko Shibata , Yoji Nishio , Seiji Funaba
发明人： Kayoko Shibata , Yoji Nishio , Seiji Funaba
IPC分类号： G11C5/06
CPC分类号： H05K1/0246 , H05K2201/10022 , H05K2201/10159
摘要： A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N−1)×Zeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N−1)×Zeffdimm/N2.
摘要翻译：存储器模块包括在引脚和总线的一端之间的尖端电阻器。多个存储器芯片在其两端之间连接到总线。终端电阻连接到总线的另一端。尖端电阻的阻抗Rs和终端电阻的终端电阻Rterm由下式给出：<？in-line-formula description =“In-line Formulas”end =“lead”？> Rs =（N-1）xZeffdimm / N和<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line-formula description =“In-line Formulas”end =“lead”？> Rterm = Zeffdimm <？in-line-formula description =“在线公式”end =“tail”？>其中N表示存储器系统中的存储器模块的数量; 和Zeffdimm，由总线和存储器芯片组成的存储芯片布置部分的有效阻抗。在存储器系统中，存储器模块以连接方式连接到主板上的存储器控制器。主板的接线阻抗Zmb由下式给出：<？in-line-formula description =“In-line formula”end =“lead”？> Zmb =（2N-1）xZeffdimm / N < 。<？in-line-formula description =“In-line Formulas”end =“tail”？>

8. 发明授权

US06661092B2 Memory module 有权
标题翻译：内存模块
公开(公告)号：US06661092B2
公开(公告)日：2003-12-09
申请号：US10205040
申请日：2002-07-25
申请人： Kayoko Shibata , Yoji Nishio
发明人： Kayoko Shibata , Yoji Nishio
IPC分类号： H01L2334
CPC分类号： G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.
摘要翻译：存储器模块设置有用作阻抗调节器的电阻器，其直接或间接地连接到C / A寄存器的输出晶体管的输出端子。该电阻调节从C / A总线的输入端子观察的C / A寄存器的输出阻抗，使得输出阻抗在从C / A寄存器输出的内部信号的工作电压范围内变得基本恒定。存储器模块还具有用作上升时间/下降时间调节器的电容器，其将内部信号的上升时间和下降时间调整到特定值，从而获得令人满意的波形。

9. 发明授权

US06873533B2 Unbuffered memory system 有权
标题翻译：无缓冲存储器系统
公开(公告)号：US06873533B2
公开(公告)日：2005-03-29
申请号：US10309072
申请日：2002-12-04
申请人： Kayoko Shibata , Yoji Nishio
发明人： Kayoko Shibata , Yoji Nishio
IPC分类号： G06F13/16 , G06F9/26 , G06F12/00 , G06F12/06 , G06F13/40 , G11C5/00 , G11C5/02 , G11C5/06 , G11C7/10
CPC分类号： G11C7/1078 , G06F13/4086 , G11C5/04 , G11C5/063
摘要： A memory module of the unbuffered type with ECC function is employed. Configuration of an internal C/A bus is set to a single T-branch topology. An output impedance of a chipset is maintained substantially constant. A capacitor for cutting high-frequency components of a C/A signal is added on a C/A bus.
摘要翻译：采用具有ECC功能的无缓冲型存储器模块。内部C / A总线的配置设置为单个T分支拓扑。芯片组的输出阻抗基本保持不变。用于切割C / A信号的高频分量的电容器被添加在C / A总线上。

10. 发明申请

US20110104852A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110104852A1
公开(公告)日：2011-05-05
申请号：US13005350
申请日：2011-01-12
申请人： Masakazu ISHINO , Hiroaki Ikeda , Kayoko Shibata
发明人： Masakazu ISHINO , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： H01L21/50
CPC分类号： H01L21/6835 , G11C5/02 , G11C5/025 , H01L23/481 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/81005 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L2924/30105 , H01L2224/81 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.
摘要翻译：半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。该器件具有插入器芯片。连接到芯片的第一内部电极形成在插入器芯片的第一表面上。连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。只要需要，接口芯片可以安装在插入器芯片的第二表面上。因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。因此，核心芯片不需要以裸芯片的形式大量存放。

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