专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07829815B2 Adjustable electrodes and coils for plasma density distribution control 有权
标题翻译：用于等离子体密度分布控制的可调电极和线圈
公开(公告)号：US07829815B2
公开(公告)日：2010-11-09
申请号：US11534495
申请日：2006-09-22
申请人： Ying-Lin Chen , Chi-An Kao , Po-Zen Chen , Yi-Li Hsiao , Chen-Hua Yu , Jean Wang , Lawrance Sheu
发明人： Ying-Lin Chen , Chi-An Kao , Po-Zen Chen , Yi-Li Hsiao , Chen-Hua Yu , Jean Wang , Lawrance Sheu
IPC分类号： B23K10/00
CPC分类号： H01J37/32568 , H01J37/32091 , H01J37/321
摘要： A adjustable upper coil or electrode for a reaction chamber apparatus useable in semiconductor processing, is constructed so that its shape may be selectively changed or so at least two portions thereof may be selectively driven at different power and/or frequencies. The adjustable upper coil or electrode, therefore, enables the plasma density distribution in the reaction chamber apparatus to be selectively controlled.
摘要翻译：用于可用于半导体处理的反应室装置的可调整的上部线圈或电极被构造成使得其形状可以选择性地改变，或者至少两个部分可以以不同的功率和/或频率被选择性地驱动。因此，可调节的上部线圈或电极能够选择性地控制反应室设备中的等离子体密度分布。

2. 发明申请

US20080083710A1 ADJUSTABLE ELECTRODES AND COILS FOR PLASMA DENSITY DISTRIBUTION CONTROL 有权
标题翻译：用于等离子体密度分布控制的可调节电极和线圈
公开(公告)号：US20080083710A1
公开(公告)日：2008-04-10
申请号：US11534495
申请日：2006-09-22
申请人： Ying-Lin Chen , Chi-An Kao , Po-Zen Chen , Yi-Li Hsiao , Chen-Hua Yu , Jean Wang , Lawrance Sheu
发明人： Ying-Lin Chen , Chi-An Kao , Po-Zen Chen , Yi-Li Hsiao , Chen-Hua Yu , Jean Wang , Lawrance Sheu
IPC分类号： B23K9/00
CPC分类号： H01J37/32568 , H01J37/32091 , H01J37/321
摘要： A adjustable upper coil or electrode for a reaction chamber apparatus useable in semiconductor processing, is constructed so that its shape may be selectively changed or so at least two portions thereof may be selectively driven at different power and/or frequencies. The adjustable upper coil or electrode, therefore, enables the plasma density distribution in the reaction chamber apparatus to be selectively controlled.
摘要翻译：用于可用于半导体处理的反应室装置的可调整的上部线圈或电极被构造成使得其形状可以选择性地改变，或者至少两个部分可以以不同的功率和/或频率被选择性地驱动。因此，可调节的上部线圈或电极能够选择性地控制反应室设备中的等离子体密度分布。

3. 发明授权

US07588946B2 Controlling system for gate formation of semiconductor devices 有权
标题翻译：半导体器件栅极形成控制系统
公开(公告)号：US07588946B2
公开(公告)日：2009-09-15
申请号：US11188324
申请日：2005-07-25
申请人： Chia-Tsung Tso , Jiun-Hong Lai , Mei-Jen Wu , Li Te Hsu , Pin Chia Su , Po-Zen Chen
发明人： Chia-Tsung Tso , Jiun-Hong Lai , Mei-Jen Wu , Li Te Hsu , Pin Chia Su , Po-Zen Chen
IPC分类号： H01L21/00
CPC分类号： H01L22/12 , H01L21/28123 , H01L21/76224 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
摘要翻译：控制半导体器件的栅极形成的方法包括通过测量隔离结构的阶跃高度来确定隔离结构的台阶高度与过蚀刻时间之间的相关性，基于台阶高度确定过蚀刻时间，以及使用过蚀刻时间。该方法可以包括蚀刻检查以测量栅极分布并微调栅极形成控制。通过测量晶片上的台阶高度均匀性并调整栅极形成工艺，也可以提高晶片内均匀性。

4. 发明申请

US20070020777A1 Controlling system for gate formation of semiconductor devices 有权
标题翻译：半导体器件栅极形成控制系统
公开(公告)号：US20070020777A1
公开(公告)日：2007-01-25
申请号：US11188324
申请日：2005-07-25
申请人： Chia-Tsung Tso , Jiun-Hong Lai , Mei-Jen Wu , Li Hsu , Pin Su , Po-Zen Chen
发明人： Chia-Tsung Tso , Jiun-Hong Lai , Mei-Jen Wu , Li Hsu , Pin Su , Po-Zen Chen
IPC分类号： H01L21/66 , H01L21/76 , H01L21/302
CPC分类号： H01L22/12 , H01L21/28123 , H01L21/76224 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
摘要翻译：控制半导体器件的栅极形成的方法包括通过测量隔离结构的阶跃高度来确定隔离结构的台阶高度与过蚀刻时间之间的相关性，基于台阶高度确定过蚀刻时间，以及使用过蚀刻时间。该方法可以包括蚀刻检查以测量栅极分布并微调栅极形成控制。通过测量晶片上的台阶高度均匀性并调整栅极形成工艺，也可以提高晶片内均匀性。

5. 发明授权

US08803271B2 Structures for grounding metal shields in backside illumination image sensor chips 有权
标题翻译：背面照明图像传感器芯片接地金属屏蔽结构
公开(公告)号：US08803271B2
公开(公告)日：2014-08-12
申请号：US13429114
申请日：2012-03-23
申请人： Zhe-Ju Liu , Chih-Cherng Jeng , Kuo-Cheng Lee , Szu-Hung Yang , Po-Zen Chen , Chi-Chin Hsu
发明人： Zhe-Ju Liu , Chih-Cherng Jeng , Kuo-Cheng Lee , Szu-Hung Yang , Po-Zen Chen , Chi-Chin Hsu
IPC分类号： H01L31/0232
CPC分类号： H01L27/14623 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464
摘要： A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate.
摘要翻译：一种器件包括具有正面和背面的半导体衬底。光敏装置设置在半导体基板的正面上。电介质层设置在半导体衬底的背面，其中电介质层在半导体衬底的背面之上。金属屏蔽层在介电层上方并与光敏器件重叠。金属插塞穿过电介质层，其中金属插头将金属屏蔽件电耦合到半导体衬底。

6. 发明授权

US07563719B2 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US07563719B2
公开(公告)日：2009-07-21
申请号：US11724284
申请日：2007-03-15
申请人： Po-Zen Chen , Tzu-Chan Weng , Chien-Chung Chen
发明人： Po-Zen Chen , Tzu-Chan Weng , Chien-Chung Chen
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31138 , H01L21/76811
摘要： A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.
摘要翻译：双镶嵌工艺。在电介质层上形成具有对应于沟槽图案的第一开口的第一光致抗蚀剂层。在第一光致抗蚀剂层上形成具有对应于小于沟槽图案的通孔图案的第二开口的第二光致抗蚀剂层并且延伸到介电层的一部分。第二光致抗蚀剂层具有与第一光致抗蚀剂层不同的材料特性。执行使用第二光致抗蚀剂作为掩模的通孔蚀刻工艺，以形成穿过介电层的通孔。进行光致抗蚀剂灰化处理以去除第二光致抗蚀剂层。执行使用第一光致抗蚀剂层作为掩模的沟槽蚀刻工艺，以在电介质层的上部形成沟槽。通孔蚀刻工艺，光致抗蚀剂灰化处理和沟槽蚀刻工艺在一个室中作为连续工艺进行。

7. 发明授权

US08872301B2 Dual profile shallow trench isolation apparatus and system 有权
标题翻译：双轮廓浅沟槽隔离装置及系统
公开(公告)号：US08872301B2
公开(公告)日：2014-10-28
申请号：US13454924
申请日：2012-04-24
申请人： Chia-Yang Hung , Po-Zen Chen , Szu-Hung Yang , Chih-Cherng Jeng , Chih-Kang Chao , I-I Cheng
发明人： Chia-Yang Hung , Po-Zen Chen , Szu-Hung Yang , Chih-Cherng Jeng , Chih-Kang Chao , I-I Cheng
IPC分类号： H01L31/18 , H01L21/311 , H01L21/66 , H01L23/48 , H01L21/762 , H01L21/02 , H01L21/8238 , H01L21/76
CPC分类号： H01L21/76229 , H01L27/1463 , H01L27/14643
摘要： The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.
摘要翻译：所呈现的原理描述了一种制造它的装置和方法，该装置是半导体电路装置，具有浅沟槽隔离特征，其界定半导体衬底上的有源区域和外围区域，以将活性区域中的结构与周边地区。围绕有源区域的浅沟槽隔离特征比围绕边缘区域的浅沟槽隔离特征浅，通过两个或更多个蚀刻步骤形成外围区域浅沟槽隔离结构。

8. 发明申请

US20130277790A1 Dual Profile Shallow Trench Isolation Apparatus and System 有权
标题翻译：双轮廓浅沟槽隔离装置和系统
公开(公告)号：US20130277790A1
公开(公告)日：2013-10-24
申请号：US13454924
申请日：2012-04-24
申请人： Chia-Yang Hung , Po-Zen Chen , Szu-Hung Yang , Chih-Cherng Jeng , Chih-Kang Chao , I-I Cheng
发明人： Chia-Yang Hung , Po-Zen Chen , Szu-Hung Yang , Chih-Cherng Jeng , Chih-Kang Chao , I-I Cheng
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76229 , H01L27/1463 , H01L27/14643
摘要： The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.
摘要翻译：所呈现的原理描述了一种制造它的装置和方法，该装置是半导体电路装置，具有浅沟槽隔离特征，其界定半导体衬底上的有源区域和外围区域，以将活性区域中的结构与周边地区。围绕有源区域的浅沟槽隔离特征比围绕边缘区域的浅沟槽隔离特征浅，通过两个或更多个蚀刻步骤形成外围区域浅沟槽隔离结构。

9. 发明申请

US20080227288A1 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US20080227288A1
公开(公告)日：2008-09-18
申请号：US11724284
申请日：2007-03-15
申请人： Po-Zen Chen , Tzu-Chan Weng , Chien-Chung Chen
发明人： Po-Zen Chen , Tzu-Chan Weng , Chien-Chung Chen
IPC分类号： H01L21/4763 , H01L21/311
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31138 , H01L21/76811
摘要： A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.
摘要翻译：双镶嵌工艺。在电介质层上形成具有对应于沟槽图案的第一开口的第一光致抗蚀剂层。在第一光致抗蚀剂层上形成具有对应于小于沟槽图案的通孔图案的第二开口的第二光致抗蚀剂层并且延伸到介电层的一部分。第二光致抗蚀剂层具有与第一光致抗蚀剂层不同的材料特性。执行使用第二光致抗蚀剂作为掩模的通孔蚀刻工艺，以形成穿过介电层的通孔。进行光致抗蚀剂灰化处理以去除第二光致抗蚀剂层。执行使用第一光致抗蚀剂层作为掩模的沟槽蚀刻工艺，以在电介质层的上部形成沟槽。通孔蚀刻工艺，光致抗蚀剂灰化处理和沟槽蚀刻工艺在一个室中作为连续工艺进行。

10. 发明申请

US20130249040A1 Structures for Grounding Metal Shields in Backside Illumination Image Sensor Chips 有权
标题翻译：背面照明图像传感器芯片接地金属屏蔽结构
公开(公告)号：US20130249040A1
公开(公告)日：2013-09-26
申请号：US13429114
申请日：2012-03-23
申请人： Zhe-Ju Liu , Chi-Cherng Jeng , Kuo-Cheng Lee , Szu-Hung Yang , Po-Zen Chen , Chi-Chin Hsu
发明人： Zhe-Ju Liu , Chi-Cherng Jeng , Kuo-Cheng Lee , Szu-Hung Yang , Po-Zen Chen , Chi-Chin Hsu
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14623 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464
摘要： A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate.
摘要翻译：一种器件包括具有正面和背面的半导体衬底。光敏装置设置在半导体基板的正面上。电介质层设置在半导体衬底的背面，其中电介质层在半导体衬底的背面之上。金属屏蔽层在介电层上方并与光敏器件重叠。金属插塞穿过电介质层，其中金属插头将金属屏蔽件电耦合到半导体衬底。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式