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1. 发明申请

US20050280113A1 Semiconductor device capable of threshold voltage adjustment by applying an external voltage 失效
标题翻译：能够通过施加外部电压来阈值电压调节的半导体器件
公开(公告)号：US20050280113A1
公开(公告)日：2005-12-22
申请号：US11008363
申请日：2004-12-09
申请人： Yil Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
发明人： Yil Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/763 , H01L21/764 , H01L21/765 , H01L21/8234 , H01L21/8242 , H01L27/02 , H01L29/00 , H01L29/06 , H01L29/78
CPC分类号： H01L29/7831 , H01L21/3065 , H01L21/3086 , H01L21/76232 , H01L21/763 , H01L21/764 , H01L21/765 , H01L21/823412 , H01L21/823481 , H01L27/0214 , H01L27/10873 , H01L29/0657 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.
摘要翻译：半导体器件具有硅衬底，其中在两个器件隔离膜之间形成有源区，并且在有源区的表面上形成栅极。硅衬底在靠近器件隔离膜的一侧上的有源区的表面下方的有源区中具有横向蚀刻的部分。绝缘膜形成在硅衬底的横向蚀刻部分上。在绝缘膜上形成导电电极，施加外部电压以调整阈值电压。器件隔离膜形成在导电电极上。在器件隔离膜和导电电极之间不存在或存在一些空穴腔。

2. 发明授权

US07301207B2 Semiconductor device capable of threshold voltage adjustment by applying an external voltage 失效
标题翻译：能够通过施加外部电压来阈值电压调节的半导体器件
公开(公告)号：US07301207B2
公开(公告)日：2007-11-27
申请号：US11008363
申请日：2004-12-09
申请人： Yil Wook Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
发明人： Yil Wook Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7831 , H01L21/3065 , H01L21/3086 , H01L21/76232 , H01L21/763 , H01L21/764 , H01L21/765 , H01L21/823412 , H01L21/823481 , H01L27/0214 , H01L27/10873 , H01L29/0657 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.
摘要翻译：半导体器件具有硅衬底，其中在两个器件隔离膜之间形成有源区，并且在有源区的表面上形成栅极。硅衬底在靠近器件隔离膜的一侧上的有源区的表面下方的有源区中具有横向蚀刻的部分。绝缘膜形成在硅衬底的横向蚀刻部分上。在绝缘膜上形成导电电极，施加外部电压以调整阈值电压。器件隔离膜形成在导电电极上。在器件隔离膜和导电电极之间不存在或存在一些空穴腔。

3. 发明授权

US07449392B2 Semiconductor device capable of threshold voltage adjustment by applying an external voltage 失效
标题翻译：能够通过施加外部电压来阈值电压调节的半导体器件
公开(公告)号：US07449392B2
公开(公告)日：2008-11-11
申请号：US11877820
申请日：2007-10-24
申请人： Yil Wook Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
发明人： Yil Wook Kim , Jun Hee Cho , Sung Eon Park , Jin Hong Ahn , Sang Don Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/7831 , H01L21/3065 , H01L21/3086 , H01L21/76232 , H01L21/763 , H01L21/764 , H01L21/765 , H01L21/823412 , H01L21/823481 , H01L27/0214 , H01L27/10873 , H01L29/0657 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.
摘要翻译：半导体器件具有硅衬底，其中在两个器件隔离膜之间形成有源区，并且在有源区的表面上形成栅极。硅衬底在靠近器件隔离膜的一侧上的有源区的表面下方的有源区中具有横向蚀刻的部分。绝缘膜形成在硅衬底的横向蚀刻部分上。在绝缘膜上形成导电电极，施加外部电压以调整阈值电压。器件隔离膜形成在导电电极上。在器件隔离膜和导电电极之间不存在或存在一些空穴腔。

4. 发明授权

US06887788B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06887788B2
公开(公告)日：2005-05-03
申请号：US10703745
申请日：2003-11-07
申请人： Jun Hee Cho , Il Wook Kim , Seok Kiu Lee , Tae Hang Ahn , Sung Eon Park
发明人： Jun Hee Cho , Il Wook Kim , Seok Kiu Lee , Tae Hang Ahn , Sung Eon Park
IPC分类号： H01L21/28 , H01L21/311 , H01L21/60 , H01L21/4763
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76897 , Y10S438/906
摘要： Disclosed is a method of manufacturing a semiconductor device. The method comprises the steps of: preparing a silicon substrate having a predetermined lower structure including a gate and a bonding area; forming an interlayer dielectric film on the top side of the substrate; forming a photosensitive film pattern, which exposes an area for providing contact, on the interlayer dielectric film; forming a contact hole exposing a bonding area of the substrate by etching the exposed part of the interlayer dielectric film; removing the photosensitive film pattern; performing a dry cleaning on the exposed bonding area of the substrate so that CF based polymer formed in the etching step is removed; and performing a nitrogen-hydrogen plasma processing on the surface of the exposed bonding area of the substrate so that oxygen polymer and remaining CF-based polymer are removed. Therefore, since hydrogen plasma processing is performed after contact etching, ohmic contact characteristics can be secured. In addition, since the hydrogen plasma processing is performed using a conventional photosensitive film strip apparatus, cost required to install and maintain an additional apparatus is not generated.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：制备具有包括栅极和接合区域的预定下部结构的硅衬底; 在所述基板的上侧形成层间电介质膜; 在所述层间绝缘膜上形成曝光用于提供接触的区域的感光膜图案; 通过蚀刻所述层间电介质膜的暴露部分形成暴露所述衬底的接合区域的接触孔; 去除感光膜图案; 在基板的暴露的接合区域上进行干洗，从而去除在蚀刻步骤中形成的CF基聚合物; 并在衬底的暴露的接合区域的表面上进行氮 - 氢等离子体处理，从而除去氧聚合物和剩余的CF基聚合物。因此，由于在接触蚀刻之后进行氢等离子体处理，因此可以确保欧姆接触特性。此外，由于使用传统的感光膜条装置执行氢等离子体处理，所以不会产生安装和维护附加装置所需的成本。

5. 发明授权

US07049230B2 Method of forming a contact plug in a semiconductor device 失效
标题翻译：在半导体器件中形成接触插塞的方法
公开(公告)号：US07049230B2
公开(公告)日：2006-05-23
申请号：US10984494
申请日：2004-11-09
申请人： Sung Eon Park
发明人： Sung Eon Park
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/28525 , H01L27/11
摘要： A contact plug is formed in a semiconductor device having a silicon substrate having a gate electrode, a junction area and an insulating interlayer. A contact hole is formed to expose the junction area. A plasma process is carried out with respect to a resultant substrate, thereby removing natural oxides created on an exposed surface of the junction area. A first silicon layer is deposited on the contact hole and on the insulating interlayer. A heat-treatment process is carried out with respect to the first silicon layer so as to grow the amorphous silicon into the epitaxial silicon. A second silicon layer is deposited on the first silicon layer.
摘要翻译：接触插塞形成在具有硅基板的半导体器件中，该硅基板具有栅电极，接合区域和绝缘中间层。形成接触孔以露出接合区域。对所得到的基板进行等离子体处理，从而除去在接合区域的暴露表面上产生的天然氧化物。第一硅层沉积在接触孔和绝缘中间层上。对第一硅层进行热处理工艺，以将非晶硅生长成外延硅。第二硅层沉积在第一硅层上。

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