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1. 发明申请

US20110081618A1 LITHO-LITHO ETCH (LLE) DOUBLE PATTERNING METHODS 审中-公开
标题翻译： LITHO-LITHO ETCH（LLE）双重图案方法
公开(公告)号：US20110081618A1
公开(公告)日：2011-04-07
申请号：US12574650
申请日：2009-10-06
申请人： Yi-Ming Wang , Pei-Lin Huang , Ying-Chung Tseng
发明人： Yi-Ming Wang , Pei-Lin Huang , Ying-Chung Tseng
IPC分类号： G03F7/20
CPC分类号： G03F7/405 , G03F7/0035 , H01L21/0273
摘要： Litho-litho-etch double patterning (LLE-DP) methods using silylation freeze technology are presented. The LLE-DP method using a silylation freeze reaction comprises providing a substrate with a first photoresist layer thereon. A first exposure process is performed defining a first latent image in a first photoresist. The first patterned structures on the substrate is developed and baked for photo-generated acid diffusion. The photo-generated acid is reacted with a silylation agent to freeze the first patterned structures. A second photoresist layer is formed overlying the substrate. A second lithography process is performed to create second patterned structures on the substrate. The first patterned structures and the second patterned structures are interlaced each other.
摘要翻译：提出了使用甲硅烷基化冷冻技术的石墨蚀刻双重图案（LLE-DP）方法。使用甲硅烷基化冷冻反应的LLE-DP方法包括在其上提供其上具有第一光致抗蚀剂层的基底。执行在第一光致抗蚀剂中限定第一潜像的第一曝光处理。显影和烘烤基底上的第一图案结构用于光致酸扩散。将光产生的酸与甲硅烷基化剂反应以冷冻第一图案化结构。第二光致抗蚀剂层形成在衬底上。执行第二光刻工艺以在衬底上产生第二图案化结构。第一图案结构和第二图案结构彼此交错。

2. 发明申请

US20100227069A1 APPARATUS FOR REDUCING COST OF DEVELOPER AND THE METHOD THEREOF 审中-公开
标题翻译：降低开发商成本的方法及其方法
公开(公告)号：US20100227069A1
公开(公告)日：2010-09-09
申请号：US12500995
申请日：2009-07-10
申请人： Chiang-Lin Shih , Pei-Lin Huang , Ying-Chung Tseng
发明人： Chiang-Lin Shih , Pei-Lin Huang , Ying-Chung Tseng
IPC分类号： B05D3/12 , B05D3/00 , B05C11/00
CPC分类号： H01L21/6715 , G03F7/3014 , G03F7/3021
摘要： An apparatus for homogenizing the developer concentration on the wafer and reducing the developer cost and the method thereof are provided in the present invention. The developer is provided on the wafer which then is spun to distribute the developer on the wafer. Next, the mechanical turbulence of the developer is produced on the wafer by the turbulence device or the mega-sonic vibrator. The apparatus is able to improve the uniformity of developer concentration, and the developer consumption is reduced.
摘要翻译：在本发明中提供了用于使晶片上的显影剂浓度均匀化并降低显影剂成本的装置及其方法。将显影剂提供在晶片上，然后旋转以将显影剂分布在晶片上。接下来，通过湍流装置或超声波振动器在晶片上产生显影剂的机械湍流。该装置能够提高显影剂浓度的均匀性，并且降低显影剂消耗。

3. 发明申请

US20110244395A1 APPARATUS AND METHOD FOR HAZE CONTROL IN A SEMICONDUCTOR PROCESS 审中-公开
标题翻译：一种半导体工艺中的雾化控制装置和方法
公开(公告)号：US20110244395A1
公开(公告)日：2011-10-06
申请号：US12754613
申请日：2010-04-06
申请人： Pei-Lin Huang , Yi-Ming Wang , Chun-Yen Huang
发明人： Pei-Lin Huang , Yi-Ming Wang , Chun-Yen Huang
IPC分类号： G03F7/20 , G03B27/42
CPC分类号： G03F7/70916 , G03F1/38
摘要： A method for haze control in a semiconductor process, includes: providing an exposure tool with a photocatalyzer coating inside and exposing a wafer in the exposure tool in the presence of activation of the photocatalyzer coating. The photocatalyzer coating may be formed within an opaque region of a reticle.
摘要翻译：一种在半导体工艺中雾度控制的方法，包括：在光催化剂涂层的活化存在下，向曝光工具提供内部的光催化剂涂层并暴露于曝光工具中的晶片。光催化剂涂层可以形成在掩模版的不透明区域内。

4. 发明授权

US08124319B2 Semiconductor lithography process 有权
标题翻译：半导体光刻工艺
公开(公告)号：US08124319B2
公开(公告)日：2012-02-28
申请号：US12758043
申请日：2010-04-12
申请人： Pei-Lin Huang , Chun-Yen Huang , Yi-Ming Wang
发明人： Pei-Lin Huang , Chun-Yen Huang , Yi-Ming Wang
IPC分类号： G03C5/00
CPC分类号： G03F7/2022 , G03F7/2028 , G03F7/70425 , G03F7/70466 , Y10S430/143
摘要： A semiconductor lithography process. A photoresist film is coated on a substrate. The photoresist film is subjected to a flood exposure to blanket expose the photoresist film across the substrate to a first radiation with a relatively lower dosage. The photoresist film is then subjected to a main exposure using a photomask to expose the photoresist film in a step and scan manner to a second radiation with a relatively higher dosage. After baking, the photoresist film is developed.
摘要翻译：半导体光刻工艺。将光致抗蚀剂膜涂覆在基材上。对光致抗蚀剂膜进行暴露曝光，以将光致抗蚀剂薄膜穿过衬底暴露于具有较低剂量的第一辐射。然后使用光掩模对光致抗蚀剂膜进行主曝光，以一步一步地将光致抗蚀剂膜曝光，并以相对较高的剂量将其扫描到第二次辐射。烘烤后，显影光致抗蚀剂膜。

5. 发明授权

US08142086B2 Semiconductor manufacturing process 有权
标题翻译：半导体制造工艺
公开(公告)号：US08142086B2
公开(公告)日：2012-03-27
申请号：US12907035
申请日：2010-10-19
申请人： Pei-Lin Huang , Yi-Ming Wang , Chun-Yen Huang
发明人： Pei-Lin Huang , Yi-Ming Wang , Chun-Yen Huang
IPC分类号： G03D5/00
CPC分类号： G03D5/00
摘要： A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer.
摘要翻译：提供半导体制造工艺。首先，提供其上形成有材料层和曝光的光致抗蚀剂层的晶片，其中晶片具有中心区域和边缘区域。此后，暴露的光致抗蚀剂层的性质是变化的，以便使得在边缘区域中的不同于中心区域的曝光光致抗蚀剂层的临界尺寸不同。在暴露的光致抗蚀剂层的边缘性质改变之后，通过使用暴露的光致抗蚀剂层作为掩模对晶片进行蚀刻处理，以便在晶片上形成具有均匀临界尺寸的图案化材料层。

6. 发明申请

US20110250540A1 SEMICONDUCTOR LITHOGRAPHY PROCESS 有权
公开(公告)号：US20110250540A1
公开(公告)日：2011-10-13
申请号：US12758043
申请日：2010-04-12
申请人： Pei-Lin Huang , Chun-Yen Huang , Yi-Ming Wang
发明人： Pei-Lin Huang , Chun-Yen Huang , Yi-Ming Wang
IPC分类号： G03F7/20
CPC分类号： G03F7/2022 , G03F7/2028 , G03F7/70425 , G03F7/70466 , Y10S430/143
摘要： A semiconductor lithography process. A photoresist film is coated on a substrate. The photoresist film is subjected to a flood exposure to blanket expose the photoresist film across the substrate to a first radiation with a relatively lower dosage. The photoresist film is then subjected to a main exposure using a photomask to expose the photoresist film in a step and scan manner to a second radiation with a relatively higher dosage. After baking, the photoresist film is developed.
摘要翻译：半导体光刻工艺。将光致抗蚀剂膜涂覆在基材上。对光致抗蚀剂膜进行暴露曝光，以将光致抗蚀剂薄膜穿过衬底暴露于具有较低剂量的第一辐射。然后使用光掩模对光致抗蚀剂膜进行主曝光，以一步一步地将光致抗蚀剂膜曝光，并以相对较高的剂量将其扫描到第二次辐射。烘烤后，显影光致抗蚀剂膜。

7. 发明申请

US20110059622A1 SEMICONDUCTOR MANUFACTURING PROCESS 有权
标题翻译：半导体制造工艺
公开(公告)号：US20110059622A1
公开(公告)日：2011-03-10
申请号：US12907035
申请日：2010-10-19
申请人： Pei-Lin Huang , Yi-Ming Wang , Chun-Yen Huang
发明人： Pei-Lin Huang , Yi-Ming Wang , Chun-Yen Huang
IPC分类号： H01L21/26
CPC分类号： G03D5/00
摘要： A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer.
摘要翻译：提供半导体制造工艺。首先，提供其上形成有材料层和曝光的光致抗蚀剂层的晶片，其中晶片具有中心区域和边缘区域。此后，暴露的光致抗蚀剂层的性质是变化的，以便使得在边缘区域中的不同于中心区域的曝光光致抗蚀剂层的临界尺寸不同。在暴露的光致抗蚀剂层的边缘性质改变之后，通过使用暴露的光致抗蚀剂层作为掩模对晶片进行蚀刻处理，以便在晶片上形成具有均匀临界尺寸的图案化材料层。

8. 发明授权

US07845868B1 Apparatus for semiconductor manufacturing process 有权
标题翻译：半导体制造工艺装置
公开(公告)号：US07845868B1
公开(公告)日：2010-12-07
申请号：US12555811
申请日：2009-09-09
申请人： Pei-Lin Huang , Yi-Ming Wang , Chun-Yen Huang
发明人： Pei-Lin Huang , Yi-Ming Wang , Chun-Yen Huang
IPC分类号： G03D5/00
CPC分类号： G03D5/00
摘要： A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer.
摘要翻译：提供半导体制造工艺。首先，提供其上形成有材料层和曝光的光致抗蚀剂层的晶片，其中晶片具有中心区域和边缘区域。此后，暴露的光致抗蚀剂层的性质是变化的，以便使得在边缘区域中的不同于中心区域的曝光光致抗蚀剂层的临界尺寸不同。在暴露的光致抗蚀剂层的边缘性质改变之后，通过使用暴露的光致抗蚀剂层作为掩模对晶片进行蚀刻处理，以便在晶片上形成具有均匀临界尺寸的图案化材料层。

9. 发明授权

US07675078B2 Pixel structure 有权
标题翻译：像素结构
公开(公告)号：US07675078B2
公开(公告)日：2010-03-09
申请号：US11162528
申请日：2005-09-14
申请人： Liang-Yuan Wang , Chih-Kwang Tzen , Pei-Lin Huang , Yi-Lung Kao , Ya-Ping Tsai , Shuenn-Jiun Tang
发明人： Liang-Yuan Wang , Chih-Kwang Tzen , Pei-Lin Huang , Yi-Lung Kao , Ya-Ping Tsai , Shuenn-Jiun Tang
IPC分类号： H01L31/0216 , H01L31/0232
CPC分类号： H01L51/5265 , H01L27/3244
摘要： A pixel structure including a control unit, an organic electro-luminescent (OEL) unit, and a filter structure is provided. The control unit is disposed on a substrate and is driven by a scan line and a data line. The OEL unit is disposed on the substrate, and includes a transparent electrode, a light-emitting layer, and a metal electrode. The transparent electrode is electrically connected with the control unit, and the light-emitting layer and the metal electrode are sequentially placed on the transparent electrode. The filter structure is sandwiched between the substrate and the OEL unit, and the filter structure includes a plurality of the first and second dielectric layers. The first and second dielectric layers are alternately stacked, and the refractive index of the first dielectric layers is different from that of the second dielectric layers.
摘要翻译：提供了包括控制单元，有机电致发光（OEL）单元和滤波器结构的像素结构。控制单元设置在基板上并由扫描线和数据线驱动。 OEL单元设置在基板上，并且包括透明电极，发光层和金属电极。透明电极与控制单元电连接，并且发光层和金属电极依次放置在透明电极上。过滤器结构被夹在基板和OEL单元之间，并且过滤器结构包括多个第一和第二电介质层。第一和第二电介质层交替层叠，并且第一电介质层的折射率不同于第二电介质层的折射率。

10. 发明申请

US20110296075A1 MOTHERBOARD USED IN SERVER COMPUTER 失效
标题翻译：在服务器计算机中使用的主板
公开(公告)号：US20110296075A1
公开(公告)日：2011-12-01
申请号：US12843047
申请日：2010-07-26
申请人： Te-Chung Kuan , Pei-Lin Huang , Chan-Kuei Hsu
发明人： Te-Chung Kuan , Pei-Lin Huang , Chan-Kuei Hsu
IPC分类号： G06F13/00
CPC分类号： G06F13/409 , G06F2213/0026
摘要： An exemplary motherboard includes a substrate, a first CPU socket provided on the substrate for receiving a first CPU, a second CPU socket provided on the substrate for receiving a second CPU, a switching circuit connected to the first CPU and the second CPU, at least one quick path interconnect (QPI) bus connecting the first CPU to the second CPU, a number of first peripheral component interconnect express (PCI-e) interfaces connected to the first CPU via a number of first wires, a number of second PCI-e interfaces connected to the second CPU via a number of second wires, and a activating chip connected to the first CPU and the second CPU via the switching circuit and configured for starting a peripheral device connected to the first PCI-e interfaces or the second PCI-e interfaces.
摘要翻译：示例性主板包括基板，设置在基板上用于接收第一CPU的第一CPU插槽，设置在基板上用于接收第二CPU的第二CPU插座，至少连接到第一CPU和第二CPU的开关电路将第一CPU连接到第二CPU的一个快速路径互连（QPI）总线，通过多个第一线连接到第一CPU的多个第一外围组件互连快递（PCI-e）接口，多个第二PCI-e 通过多个第二线连接到第二CPU的接口;以及激活芯片，其经由切换电路连接到第一CPU和第二CPU，并且被配置为启动连接到第一PCI-e接口或第二PCI-e接口的外围设备， e接口。

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