专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06496429B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06496429B2
公开(公告)日：2002-12-17
申请号：US09988173
申请日：2001-11-19
申请人： Yasumitsu Murai , Tetsushi Tanizaki , Masaru Haraguchi
发明人： Yasumitsu Murai , Tetsushi Tanizaki , Masaru Haraguchi
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C29/1201 , G11C29/48
摘要： A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.
摘要翻译：将备用存储单元数据输入/输出到半导体存储器件的外部的备用数据端子和用于输入/输出正常存储单元数据的端子彼此分开设置。在测试模式中，数据终端并联连接到内部数据线对，并且备用数据线对耦合到备用数据终端。因此，可以缩短用于检测半导体存储器件中的有缺陷的位的测试时间。

2. 发明授权

US06779139B2 Circuit for reducing test time and semiconductor memory device including the circuit 有权
标题翻译：降低测试时间的电路和包括电路的半导体存储器件
公开(公告)号：US06779139B2
公开(公告)日：2004-08-17
申请号：US09845494
申请日：2001-05-01
申请人： Masaru Haraguchi , Katsumi Dosaka , Tetsushi Tanizaki
发明人： Masaru Haraguchi , Katsumi Dosaka , Tetsushi Tanizaki
IPC分类号： G11C2900
CPC分类号： G11C29/44 , G01R31/318566 , G11C29/38
摘要： A semiconductor memory device includes: a determination section; an expected value control section; and an accumulation section. The determination section determines coincidence/non-coincidence between input data and an expected value. The expected value control section catches a read expected value in a read operation only. The accumulation section catches a determination result according to an accumulation-transmission signal. When the accumulation-transmission signal is in a transmission state, a determination result is caught, while when the accumulation-transmission signal enters an accumulation state, the next determination result is caught in a case of coincidence determination and once a non-coincidence determination result is caught, thereafter the non-coincidence determination result continues to be held.
摘要翻译：半导体存储器件包括：确定部分; 预期价值控制部分; 和积累部分。确定部分确定输入数据与期望值之间的一致/不一致。期望值控制部分仅在读取操作中捕获读取期望值。累积部根据累积发送信号来取得判定结果。当累积发送信号处于发送状态时，判断结果被捕获，而当累计发送信号进入累加状态时，在一致判断的情况下，下一个确定结果被捕获，并且一旦不一致确定结果被捕获，此后不合格确定结果继续保持。

3. 发明授权

US06704229B2 Semiconductor test circuit for testing a semiconductor memory device having a write mask function 失效
标题翻译：半导体测试电路，用于测试具有写掩码功能的半导体存储器件
公开(公告)号：US06704229B2
公开(公告)日：2004-03-09
申请号：US10122365
申请日：2002-04-16
申请人： Masaru Haraguchi , Tetsushi Tanizaki
发明人： Masaru Haraguchi , Tetsushi Tanizaki
IPC分类号： G11C700
CPC分类号： G11C29/38 , G11C7/1006 , G11C29/36
摘要： In a test circuit for testing an eDRAM provided with a write mask function, eight internal expected values are generated based on a prescribed read data signal among read data signals of one unit of write mask (i.e., eight). Determination is performed as to whether the eight read data signals and the eight internal expected values respectively match or not, and when they match, the eight memory cells are determined to be normal. Thus, a multi-bit test can be performed even when a test pattern is written using a write mask function.
摘要翻译：在用于测试具有写掩码功能的eDRAM的测试电路中，基于一个写入掩码（即八个）单位的读取数据信号中的规定的读取数据信号产生八个内部预期值。执行关于八个读取数据信号和八个内部期望值是否分别匹配的确定，并且当它们匹配时，确定八个存储器单元是正常的。因此，即使当使用写入掩码功能写入测试图案时，也可以执行多位测试。

4. 发明授权

US07007215B2 Test circuit capable of testing embedded memory with reliability 失效
公开(公告)号：US07007215B2
公开(公告)日：2006-02-28
申请号：US10173266
申请日：2002-06-18
申请人： Mitsuya Kinoshita , Tetsushi Tanizaki , Masaru Haraguchi , Katsumi Dosaka
发明人： Mitsuya Kinoshita , Tetsushi Tanizaki , Masaru Haraguchi , Katsumi Dosaka
IPC分类号： G01R31/30
CPC分类号： G11C29/56012 , G01R31/318572 , G01R31/31858 , G11C29/56
摘要： A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.

5. 发明申请

US20080181047A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080181047A1
公开(公告)日：2008-07-31
申请号：US12010674
申请日：2008-01-29
申请人： Masaru Haraguchi , Tokuya Osawa
发明人： Masaru Haraguchi , Tokuya Osawa
IPC分类号： G11C8/18
CPC分类号： G11C29/02 , G11C29/022 , G11C29/023
摘要： A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.
摘要翻译：本发明的半导体器件包括确定相移量的DLL电路，在测试模式时将相移量移位预定相位的运算电路，设定相移量的寄存器以及移相量的发送电路一个阶段到设定阶段发送或接收一个信号。传输电路具有第一移相器，其将第一信号移位到设定相位，第一双向缓冲器，以测试模式时间回送第一信号;第二移相器，其将从第一双向缓冲器输出的信号相移第三移相器，其将第三信号相移，在测试模式时间使第三信号回路的第二双向缓冲器，使从第二双向缓冲器输出的信号相移的第四移相器;以及FIFO，取出第二移相器或第四移相器的输出信号。

6. 发明授权

US06781903B2 Semiconductor memory device with power consumption reduced in non-data-access 失效
公开(公告)号：US06781903B2
公开(公告)日：2004-08-24
申请号：US10409593
申请日：2003-04-09
申请人： Atsuo Mangyo , Masaru Haraguchi , Akira Yamazaki
发明人： Atsuo Mangyo , Masaru Haraguchi , Akira Yamazaki
IPC分类号： G11C700
CPC分类号： G11C11/40611 , G11C7/1048 , G11C7/18 , G11C11/406 , G11C11/4097 , G11C2207/002 , G11C2211/4067 , G11C2211/4068
摘要： A semiconductor memory device includes a first data line electrically connected to selected one of a plurality of memory cells in response to activation of a word line, a second data line provided hierarchically with respect to the first data line, a read circuit provided between the first data line and the second data line to drive the second data line to a fixed voltage with a driving power according to a voltage on the first data line at the time of data reading, and a voltage supply control circuit for supplying a predetermined voltage to the second data line in response to a precharge/equalize instruction. The voltage supply control circuit includes a voltage supply stop circuit disconnecting the second data line from the predetermined voltage in a predetermined period except for the time of data reading.

7. 发明授权

US06449198B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06449198B1
公开(公告)日：2002-09-10
申请号：US09717375
申请日：2000-11-22
申请人： Kei Hamade , Takeshi Hamamoto , Masaru Haraguchi , Yasuhiro Konishi
发明人： Kei Hamade , Takeshi Hamamoto , Masaru Haraguchi , Yasuhiro Konishi
IPC分类号： G11C700
CPC分类号： G11C7/1048 , G11C11/4096 , G11C11/4097
摘要： In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.
摘要翻译：在SDRAM中，选择器根据列块选择信号和字配置选择信号来选择四个全局IO线对中的一个，并将所选择的全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对在规定的时间内。由于全局IO线对的均衡可以在全局IO线对以脉冲方式连接到前置放大器的输入/输出节点对之后立即开始，所以可以将全局IO线的更长的均衡周期放在一边，以便读取操作可以稳定。

8. 发明授权

US07983112B2 Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system 有权
标题翻译：通过DDR系统向外部存储器发送信号或从外部存储器接收信号的半导体装置
公开(公告)号：US07983112B2
公开(公告)日：2011-07-19
申请号：US12010674
申请日：2008-01-29
申请人： Masaru Haraguchi , Tokuya Osawa
发明人： Masaru Haraguchi , Tokuya Osawa
IPC分类号： G11C8/16
CPC分类号： G11C29/02 , G11C29/022 , G11C29/023
摘要： A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.
摘要翻译：本发明的半导体器件包括确定相移量的DLL电路，在测试模式时将相移量移位预定相位的运算电路，设定相移量的寄存器以及移相量的发送电路一个阶段到设定阶段发送或接收一个信号。传输电路具有第一移相器，其将第一信号移位到设定相位，第一双向缓冲器，以测试模式时间回送第一信号;第二移相器，其将从第一双向缓冲器输出的信号相移第三移相器，其将第三信号相移，在测试模式时间使第三信号回路的第二双向缓冲器，使从第二双向缓冲器输出的信号相移的第四移相器;以及FIFO，取出第二移相器或第四移相器的输出信号。

9. 发明申请

US20100257324A1 INTERFACE CIRCUIT 审中-公开
标题翻译：接口电路
公开(公告)号：US20100257324A1
公开(公告)日：2010-10-07
申请号：US12751810
申请日：2010-03-31
申请人： Tokuya Osawa , Masaru Haraguchi , Yoshikazu Morooka , Hiroshi Kinoshita
发明人： Tokuya Osawa , Masaru Haraguchi , Yoshikazu Morooka , Hiroshi Kinoshita
IPC分类号： G06F12/00
CPC分类号： G11C8/08 , G11C7/1066
摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.
摘要翻译：可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。根据检测结果，接口电路单元接收传送数据并初始化接收地址。当后同步码结束时，数据选通信号变为高阻态。数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。

10. 发明申请

US20080068040A1 SEMICONDUCTOR DEVICE AND IMPEDANCE ADJUSTING METHOD THEREOF 失效
标题翻译：半导体器件及其阻抗调整方法
公开(公告)号：US20080068040A1
公开(公告)日：2008-03-20
申请号：US11852032
申请日：2007-09-07
申请人： Chikayoshi Morishima , Tokuya Osawa , Masaru Haraguchi , Yoshihiro Yamashita
发明人： Chikayoshi Morishima , Tokuya Osawa , Masaru Haraguchi , Yoshihiro Yamashita
IPC分类号： H03K19/0175
CPC分类号： H03K19/0005 , H03K19/018578
摘要： There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.
摘要翻译：提供了一种包括输出缓冲电路的半导体器件，其减少用于阻抗调整的电路占据的面积，并允许高速阻抗调节。在阻抗测量电路中，测量与构成输出缓冲电路的多个晶体管尺寸相同尺寸的参考晶体管的尺寸相等的阻抗值。基于来自阻抗测量电路的测量结果，阻抗代码产生电路将对应于基准晶体管的阻抗值的阻抗代码输出到输出缓冲器代码产生电路。输出缓冲器代码产生电路通过执行算术运算处理产生用于调节输出缓冲器电路的阻抗的输出缓冲器代码，以提供基于阻抗代码的物镜阻抗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式