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1. 发明授权

US06461966B1 Method of high density plasma phosphosilicate glass process on pre-metal dielectric application for plasma damage reducing and throughput improvement 有权
标题翻译：高密度等离子体磷硅酸盐玻璃工艺对金属前介电应用的方法，用于等离子体损伤降低和生产率提高
公开(公告)号：US06461966B1
公开(公告)日：2002-10-08
申请号：US10017954
申请日：2001-12-14
申请人： Yao-Hsiang Chen , Chu-Yun Fu , Syung-Ming Jang
发明人： Yao-Hsiang Chen , Chu-Yun Fu , Syung-Ming Jang
IPC分类号： H01L21311
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/02164 , H01L21/31625
摘要： A method of forming a composite dielectric layer comprising the following steps. A structure having at least two semiconductor structures separated by a gap therebetween is provided. A first dielectric layer is formed over the structure, the two semiconductor structures and within the gap between the two semiconductor structures to a thickness as least as high as the top of the semiconductor structures by a first high density plasma (HDP) process. The first HDP process having a first high bias RF power, a low first deposition: sputter ratio and a first chucking bias voltage. A second dielectric layer is then formed over the first dielectric layer by a second HDP process to form the composite dielectric layer. The second HDP process having: a second bias RF power that is less than the first bias RF power; a second deposition: sputter ratio that is greater than the first deposition: sputter ratio; and a second chucking bias voltage that is zero.
摘要翻译：一种形成复合电介质层的方法，包括以下步骤。提供了具有由它们之间的间隙隔开的至少两个半导体结构的结构。第一介电层通过第一高密度等离子体（HDP）工艺形成在半导体结构的两个半导体结构之间，并且在两个半导体结构之间的间隙内至少与半导体结构的顶部一样高的厚度。第一HDP工艺具有第一高偏压RF功率，低的第一沉积：溅射比和第一夹持偏置电压。然后通过第二HDP工艺在第一介电层上形成第二介电层以形成复合介电层。第二HDP处理具有：小于第一偏置RF功率的第二偏置RF功率; 第二沉积：溅射比大于第一沉积：溅射比; 和第二夹持偏置电压为零。

2. 发明授权

US07265009B2 HDP-CVD methodology for forming PMD layer 有权
标题翻译：用于形成PMD层的HDP-CVD方法
公开(公告)号：US07265009B2
公开(公告)日：2007-09-04
申请号：US11067043
申请日：2005-02-24
申请人： Yao-Hsiang Chen
发明人： Yao-Hsiang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/76801 , C23C16/509 , H01L21/02129 , H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/76837 , H01L21/823871 , H01L29/78 , H01L29/7843
摘要： A method of forming an HDP-CVD pre-metal dielectric (PMD) layer to reduce plasma damage and/or preferential sputtering at a reduced a thermal budget including providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a PMD layer according to an HDP-CVD process over the at least two overlying semiconductor structures without applying a chucking bias Voltage to hold the semiconductor substrate.
摘要翻译：一种形成HDP-CVD预金属电介质（PMD）层的方法，以减少热预算来减少等离子体损伤和/或优先溅射，包括提供包括由间隙隔开的至少两个上覆半导体结构的半导体衬底; 根据HDP-CVD工艺在所述至少两个上覆半导体结构上形成PMD层，而不施加夹持偏置电压以保持半导体衬底。

3. 发明申请

US20060189060A1 HDP-CVD methodology for forming PMD layer 有权
标题翻译：用于形成PMD层的HDP-CVD方法
公开(公告)号：US20060189060A1
公开(公告)日：2006-08-24
申请号：US11067043
申请日：2005-02-24
申请人： Yao-Hsiang Chen
发明人： Yao-Hsiang Chen
IPC分类号： H01L21/8238 , H01L21/44 , H01L21/31
CPC分类号： H01L21/76801 , C23C16/509 , H01L21/02129 , H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/76837 , H01L21/823871 , H01L29/78 , H01L29/7843
摘要： A method of forming an HDP-CVD pre-metal dielectric (PMD) layer to reduce plasma damage and/or preferential sputtering at a reduced a thermal budget including providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a PMD layer according to an HDP-CVD process over the at least two overlying semiconductor structures without applying a chucking bias Voltage to hold the semiconductor substrate.
摘要翻译：一种形成HDP-CVD预金属电介质（PMD）层的方法，以减少热预算来减少等离子体损伤和/或优先溅射，包括提供包括由间隙隔开的至少两个上覆半导体结构的半导体衬底; 根据HDP-CVD工艺在所述至少两个上覆半导体结构上形成PMD层，而不施加夹持偏置电压以保持半导体衬底。

4. 发明授权

US08624362B2 IC wafer having electromagnetic shielding effects and method for making the same 有权
标题翻译：具有电磁屏蔽效果的IC晶片及其制造方法
公开(公告)号：US08624362B2
公开(公告)日：2014-01-07
申请号：US13219468
申请日：2011-08-26
申请人： Yao-Hsiang Chen , Tsang-Yu Liu , Yen-Shih Ho , Shu-Ming Chang
发明人： Yao-Hsiang Chen , Tsang-Yu Liu , Yen-Shih Ho , Shu-Ming Chang
IPC分类号： H01L21/60 , H01L23/498
CPC分类号： H01L23/552 , H01L21/71 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0346 , H01L2224/0361 , H01L2224/0401 , H01L2224/05572 , H01L2224/06155 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13144 , H01L2924/00013 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.
摘要翻译： IC晶片和IC晶片的制造方法，IC晶片包括具有多个焊盘和设置在其上的绝缘层的集成电路层，多个贯穿相应于焊盘的绝缘层的通孔，分别用于封装层的注入和形成在绝缘层的顶表面上并与用于电磁结构的集成电路层的焊盘电隔离的电磁屏蔽层。因此，集成电路不需要任何进一步的屏蔽掩模，从而简化制造。此外，通孔的设计有助于进一步的包装过程。

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