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    • 9. 发明申请
    • Asymmetric spacers and asymmetric source/drain extension layers
    • 非对称隔离层和不对称源极/漏极延伸层
    • US20060170016A1
    • 2006-08-03
    • US11047946
    • 2005-02-01
    • Leo MathewYang DuBich-Yen NguyenVoon-Yew Thean
    • Leo MathewYang DuBich-Yen NguyenVoon-Yew Thean
    • H01L29/78H01L21/336
    • H01L29/4983H01L29/165H01L29/517H01L29/665H01L29/6653H01L29/6656H01L29/66628H01L29/66659H01L29/7843
    • A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
    • 提供一种形成半导体器件的方法,其中设置有其上设置有栅介质层(106)的衬底(102),并且在栅极介电层上形成具有第一和第二侧壁的栅电极(116)。 分别在第一和第二侧壁附近形成第一(146)和第二(150)延伸间隔结构。 在所得装置中:(a)第一和第二延伸间隔结构具有不同的尺寸; (b)第一和第二延伸间隔结构包括第一和第二不同材料; (c)该器件具有不对称的源极/漏极延伸部分(162); 和/或(d)所述器件具有设置在所述第一延伸间隔物结构和所述栅电极之间的氧化物层(160),以及(i)所述器件在所述第二延伸间隔物结构和所述栅电极之间没有设置介电层, 或者(ii)该器件具有设置在第二延伸间隔物结构和栅极之间的第二介电层,并且第一介电层基本上比第二介电层更厚。
    • 10. 发明授权
    • Method and circuit for multiplying signals with a transistor having more than one independent gate structure
    • 用于将信号与具有多于一个独立栅极结构的晶体管相乘的方法和电路
    • US06969656B2
    • 2005-11-29
    • US10728621
    • 2003-12-05
    • Yang DuLeo Mathew
    • Yang DuLeo Mathew
    • H01L21/336H01L21/8234H01L21/84H01L29/423H01L29/786
    • H01L29/42384H01L21/823437H01L21/84H01L29/66818H01L29/785
    • A double gate semiconductor device (2006) is used beneficially as a multiplier (2000). The double gate semiconductor device (2006) has a lateral fin (105) as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between the two gates. To increase drive current, multiple transistors are easily connected in parallel by having a continuous fin structure (2106) with alternating source/drain terminals (2120, 2122, 2124, 2126) in which the sources are connected together and the drains are connected together. Gates (2116, 2110) are positioned between each pair of adjacent source/drain terminals and electrically connected together. The multiplier (2000) may also be used as a mixer and further as a phase detector.
    • 双门半导体器件(2006)有效地用作乘法器(2000)。 双栅极半导体器件(2006)具有作为沟道区域的侧鳍(105),栅极的两侧具有彼此相对的栅极。 翅片的横向定位在两个门之间提供对称性。 为了增加驱动电流,多个晶体管通过具有连续的鳍状结构(2106)容易地并联连接,其中源极连接在一起并且漏极连接在一起,其具有交替的源极/漏极端子(2120,2122,2124,2126)。 门(2116,2110)位于每对相邻的源极/漏极端子之间并电连接在一起。 乘法器(2000)也可以用作混频器,并且还可以用作相位检测器。