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1. 发明申请

US20080057645A1 FABRICATING METHOD OF MOSFET WITH THICK GATE DIELECTRIC LAYER 审中-公开
标题翻译：具有厚栅介质层的MOSFET的制造方法
公开(公告)号：US20080057645A1
公开(公告)日：2008-03-06
申请号：US11831443
申请日：2007-07-31
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/513 , H01L29/7833
摘要： The fabricating method of a thick gate dielectric layer transistor is disclosed. A substrate including a first and a second regions and isolation structures is provided. A pad layer and a masking layer are formed on the substrate between the isolation structures. After the masking layer and the pad layer in the second region are removed, a dielectric layer and a conductive layer are sequentially formed on the substrate. The conductive layer, the dielectric layer and the pad layer are patterned to form a first gate structure in the first region and a second gate structure in the second region. A first source region and a first drain region are respectively formed in the substrate adjacent to the first gate structure, and a second source region and a second drain region are formed respectively in the substrate adjacent to the second gate structure.
摘要翻译：公开了一种厚栅介质层晶体管的制造方法。提供了包括第一和第二区域和隔离结构的衬底。在隔离结构之间的衬底上形成衬垫层和掩模层。在除去第二区域中的掩模层和焊盘层之后，在衬底上依次形成介电层和导电层。将导电层，电介质层和焊盘层图案化以在第一区域中形成第一栅极结构，在第二区域中形成第二栅极结构。第一源极区域和第一漏极区域分别形成在与第一栅极结构相邻的衬底中，并且第二源极区域和第二漏极区域分别形成在与第二栅极结构相邻的衬底中。

2. 发明申请

US20080017917A1 NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20080017917A1
公开(公告)日：2008-01-24
申请号：US11778226
申请日：2007-07-16
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
IPC分类号： H01L29/788 , H01L21/3205
CPC分类号： H01L29/7881 , H01L21/76829 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory having an isolation structure, a floating gate transistor, a specific dielectric layer and an erase gate is provided. The isolation structure is disposed in a substrate to define an active region. The floating gate transistor having a floating gate, a tunneling dielectric layer, a first source/drain region and a second source/drain region is disposed on the substrate. The floating gate is disposed on the substrate and runs across the active region. The tunneling dielectric layer is disposed between the floating gate and the substrate. The first source/drain region and the second source/drain region are disposed in the substrate at the sides of the floating gate, respectively. The specific dielectric layer serves as an inter-layer dielectric layer, which is disposed on top of the floating gate. The erase gate is a conductive plug disposed upon the specific dielectric layer.
摘要翻译：提供具有隔离结构的非易失性存储器，浮置栅极晶体管，特定介质层和擦除栅极。隔离结构设置在衬底中以限定有源区。具有浮置栅极，隧道电介质层，第一源极/漏极区域和第二源极/漏极区域的浮置栅极晶体管设置在衬底上。浮置栅极设置在衬底上并跨越有源区域。隧道介电层设置在浮置栅极和衬底之间。第一源极/漏极区域和第二源极/漏极区域分别设置在浮置栅极的侧面的衬底中。比电介质层用作层间电介质层，其设置在浮动栅极的顶部。擦除栅极是设置在特定电介质层上的导电插塞。

3. 发明授权

US07551494B2 Single-poly non-volatile memory device and its operation method 有权
标题翻译：单聚多边形非易失性存储器件及其操作方法
公开(公告)号：US07551494B2
公开(公告)日：2009-06-23
申请号：US12125912
申请日：2008-05-22
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
IPC分类号： G11C7/00
CPC分类号： G11C16/0475 , G11C16/0466 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/6656 , H01L29/7881 , H01L29/7923
摘要： A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.
摘要翻译：提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储单元。单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P +源极掺杂区域和P +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。氮化硅层用作电荷捕获层。

4. 发明申请

US20080293199A1 SINGLE-POLY NON-VOLATILE MEMORY DEVICE AND ITS OPERATION METHOD 有权
标题翻译：单波非易失性存储器件及其操作方法
公开(公告)号：US20080293199A1
公开(公告)日：2008-11-27
申请号：US12125912
申请日：2008-05-22
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
IPC分类号： H01L21/336
CPC分类号： G11C16/0475 , G11C16/0466 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/6656 , H01L29/7881 , H01L29/7923
摘要： A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.
摘要翻译：提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储单元。单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P +源极掺杂区域和P +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。氮化硅层用作电荷捕获层。

5. 发明申请

US20080019165A1 SEMICONDUCTOR CAPACITOR, ONE TIME PROGRAMMABLE MEMORY CELL AND FABRICATING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：半导体电容器，一次可编程存储器单元及其制作方法及其工作方法
公开(公告)号：US20080019165A1
公开(公告)日：2008-01-24
申请号：US11697070
申请日：2007-04-05
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
IPC分类号： G11C17/04 , H01L21/8246 , H01L27/115 , H01L29/94
CPC分类号： G11C17/04 , G11C2216/26 , H01L27/112 , H01L27/11206 , H01L29/94
摘要： A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.
摘要翻译：本文提供了具有栅极，栅极介电层，源极区域，漏极区域，电容器电介质层和导电插塞的一次性可编程存储器单元。栅介质层设置在基板上。栅极设置在栅极电介质层上。源极区域和漏极区域分别设置在栅极的侧面的基板中。电容器介质层设置在源极区域上。电容器介电层是电阻保护氧化物层或自对准的自对准硅化物阻挡层。导电插头设置在电容器电介质层上。导电插头用作电容器的第一电极，源区域用作电容器的第二电极。一次性可编程存储器（OTP）单元通过使电容器介质层击穿而被编程。

6. 发明申请

US20070109872A1 SINGLE-POLY NON-VOLATILE MEMORY DEVICE AND ITS OPERATION METHOD 审中-公开
标题翻译：单波非易失性存储器件及其操作方法
公开(公告)号：US20070109872A1
公开(公告)日：2007-05-17
申请号：US11380662
申请日：2006-04-28
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/4234 , H01L29/6656 , H01L29/7881 , H01L29/7923
摘要： A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.
摘要翻译：提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储单元。单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P < SUP + +源极掺杂区域和P + +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。氮化硅层用作电荷捕获层。

7. 发明申请

US20070109860A1 SINGLE-POLY NON-VOLATILE MEMORY DEVICE AND ITS OPERATION METHOD 审中-公开
标题翻译：单波非易失性存储器件及其操作方法
公开(公告)号：US20070109860A1
公开(公告)日：2007-05-17
申请号：US11277365
申请日：2006-03-24
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/4234 , H01L29/6656 , H01L29/7881 , H01L29/7923
摘要： A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layer on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layer include a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer. The metallurgical junction of P-type drain and N-type well locates underneath the ONO sidewall.
摘要翻译：提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储单元。单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P +源极掺杂区域和P +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。氮化硅层用作电荷捕获层。 P型漏极和N型阱的冶金结点位于ONO侧壁下方。

8. 发明申请

US20070108508A1 SINGLE-POLY NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：单一非易失性存储器件
公开(公告)号：US20070108508A1
公开(公告)日：2007-05-17
申请号：US11277364
申请日：2006-03-24
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Shih-Jye Shen , Ya-Chin King , Ching-Hsiang Hsu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： G11C16/0475 , G11C16/0466 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/4234 , H01L29/6656 , H01L29/7881 , H01L29/7923
摘要： A single-poly, P-channel non-volatile memory (NVM) cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and the N well, an ONO layers on sidewalls of the gate, a P+ source doping region and a P+ drain doping region. The ONO layers include a first oxide layer deposited on the sidewalls of the gate and extends to the N well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer. The metallurgical junction of P-type drain and N-type well locates underneath the sidewall ONO layers.
摘要翻译：提供了与纳米级半导体制造工艺完全兼容的单聚磷，P沟道非易失性存储器（NVM）单元。单通道P沟道非易失性存储单元包括N阱，形成在N阱上的栅极，栅极和N阱之间的栅极电介质层，栅极侧壁上的ONO层，P < SUP + +源极掺杂区域和P + +漏极掺杂区域。 ONO层包括沉积在栅极的侧壁上并延伸到N阱的第一氧化物层和形成在第一氧化物层上的氮化硅层。氮化硅层用作电荷捕获层。 P型漏极和N型阱的冶金结点位于侧壁ONO层的下方。

9. 发明授权

US08384155B2 Semiconductor capacitor 有权
标题翻译：半导体电容
公开(公告)号：US08384155B2
公开(公告)日：2013-02-26
申请号：US11697070
申请日：2007-04-05
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
IPC分类号： H01L29/94
CPC分类号： G11C17/04 , G11C2216/26 , H01L27/112 , H01L27/11206 , H01L29/94
摘要： A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned salicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.
摘要翻译：本文提供了具有栅极，栅极介电层，源极区域，漏极区域，电容器电介质层和导电插塞的一次性可编程存储器单元。栅介质层设置在基板上。栅极设置在栅极电介质层上。源极区域和漏极区域分别设置在栅极的侧面的基板中。电容器介质层设置在源极区域上。电容器介电层是电阻保护氧化物层或自对准的自对准硅化物阻挡层。导电插头设置在电容器电介质层上。导电插头用作电容器的第一电极，源区域用作电容器的第二电极。一次性可编程存储器（OTP）单元通过使电容器介质层击穿而被编程。

10. 发明申请

US20120099361A1 SEMICONDUCTOR CAPACITOR, ONE TIME PROGRAMMABLE MEMORY CELL AND FABRICATING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：半导体电容器，一次可编程存储器单元及其制作方法及其工作方法
公开(公告)号：US20120099361A1
公开(公告)日：2012-04-26
申请号：US13338632
申请日：2011-12-28
申请人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
发明人： Chrong-Jung Lin , Hsin-Ming Chen , Ya-Chin King
IPC分类号： G11C17/04
CPC分类号： G11C17/04 , G11C2216/26 , H01L27/112 , H01L27/11206 , H01L29/94
摘要： A one time programmable memory cell having a gate, a gate dielectric layer, a source region, a drain region, a capacitor dielectric layer and a conductive plug is provided herein. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The source region and the drain region are disposed in the substrate at the sides of the gate, respectively. The capacitor dielectric layer is disposed on the source region. The capacitor dielectric layer is a resistive protection oxide layer or a self-aligned silicide block layer. The conductive plug is disposed on the capacitor dielectric layer. The conductive plug is served as a first electrode of a capacitor and the source region is served as a second electrode of the capacitor. The one time programmable memory (OTP) cell is programmed by making the capacitor dielectric layer breakdown.
摘要翻译：本文提供了具有栅极，栅极介电层，源极区域，漏极区域，电容器电介质层和导电插塞的一次性可编程存储器单元。栅介质层设置在基板上。栅极设置在栅极电介质层上。源极区域和漏极区域分别设置在栅极的侧面的基板中。电容器介质层设置在源极区域上。电容器介电层是电阻保护氧化物层或自对准硅化物阻挡层。导电插头设置在电容器电介质层上。导电插头用作电容器的第一电极，源区域用作电容器的第二电极。一次性可编程存储器（OTP）单元通过使电容器介质层击穿而被编程。

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