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1. 发明申请

US20120194253A1 High Voltage Tolerant Differential Receiver 有权
标题翻译：高电压容差差分接收器
公开(公告)号：US20120194253A1
公开(公告)日：2012-08-02
申请号：US13014738
申请日：2011-01-27
申请人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
发明人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
IPC分类号： H03L5/00 , G06G7/16
CPC分类号： G06F13/4072 , H03K19/018528
摘要： A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.
摘要翻译：高耐压差分接收器电路包括分压器梯形图，其可操作地分压大于分压器梯形图的阈值电压的半差分输入信号。通路电路用于接收低于分压器梯形图的阈值电压的差分输入信号。来自分压器梯形图和通过门电路的输出提供给单独的比较器。来自比较器的输出被组合以在接收器电路的电压域中产生信号。

2. 发明授权

US08076963B2 Delay-locked loop having a delay independent of input signal duty cycle variation 有权
标题翻译：延迟锁定环路具有独立于输入信号占空比变化的延迟
公开(公告)号：US08076963B2
公开(公告)日：2011-12-13
申请号：US12559749
申请日：2009-09-15
申请人： Xuhao Huang , Xiaohong Quan
发明人： Xuhao Huang , Xiaohong Quan
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/13 , H03K5/133 , H03K5/1565 , H03K2005/00136
摘要： A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.
摘要翻译：延迟锁定环（DLL）使用延迟线将第一信号延迟“延迟时间”，从而产生第二信号。电容器以从第一信号的第一边缘开始的第一速率充电并持续到第二信号的边沿。然后电容器以第二速率放电，直到第一信号的另一个边沿。控制回路控制延迟时间，使得电容器的充电量与电容器放电量相同。延迟时间是恒定的并且基本上与第一信号的占空比的变化无关。在一个示例中，通过相对于第一信号占空比的变化按比例改变第一速率来实现占空比失真消除。在另一示例中，第一和第二速率与第一信号的占空比无关。

3. 发明授权

US08680891B2 High voltage tolerant differential receiver 有权
标题翻译：高耐压差分接收器
公开(公告)号：US08680891B2
公开(公告)日：2014-03-25
申请号：US13014738
申请日：2011-01-27
申请人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
发明人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
IPC分类号： H03K5/22 , G06F13/40
CPC分类号： G06F13/4072 , H03K19/018528
摘要： A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.
摘要翻译：高耐压差分接收器电路包括分压器梯形图，其可操作地分压大于分压器梯形图的阈值电压的半差分输入信号。通路电路用于接收低于分压器梯形图的阈值电压的差分输入信号。来自分压器梯形图和通过门电路的输出提供给单独的比较器。来自比较器的输出被组合以在接收器电路的电压域中产生信号。

4. 发明授权

US08446204B2 High voltage tolerant receiver 有权
标题翻译：高耐压接收机
公开(公告)号：US08446204B2
公开(公告)日：2013-05-21
申请号：US13014740
申请日：2011-01-27
申请人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
发明人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
IPC分类号： H03L5/00 , H03K3/00
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.
摘要翻译：高耐压单端接收器电路包括分压器，其可操作地将大于分压器的阈值电压的半个单端输入信号分频。通路门电路用于接收低于分压器的阈值电压的单端信号。来自分压器的输出耦合到修改的施密特触发电路的第一输入端，以控制施密特触发电路的高阈值电平。来自通路电路的输出耦合到修改的施密特触发电路的第二输入，以控制施密特触发电路的低阈值电平。

5. 发明申请

US20120194254A1 High Voltage Tolerant Receiver 有权
标题翻译：高耐压接收器
公开(公告)号：US20120194254A1
公开(公告)日：2012-08-02
申请号：US13014740
申请日：2011-01-27
申请人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
发明人： Ankit Srivastava , Xuhao Huang , Xiaohong Quan
IPC分类号： H03L5/00
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.
摘要翻译：高耐压单端接收器电路包括分压器，其可操作地将大于分压器的阈值电压的半个单端输入信号分频。通路门电路用于接收低于分压器的阈值电压的单端信号。来自分压器的输出耦合到修改的施密特触发电路的第一输入端，以控制施密特触发电路的高阈值电平。来自通路电路的输出耦合到修改的施密特触发电路的第二输入，以控制施密特触发电路的低阈值电平。

6. 发明申请

US20110063005A1 DELAY-LOCKED LOOP HAVING A DELAY INDEPENDENT OF INPUT SIGNAL DUTY CYCLE VARIATION 有权
标题翻译：具有延迟的延迟环路输入信号周期变化独立
公开(公告)号：US20110063005A1
公开(公告)日：2011-03-17
申请号：US12559749
申请日：2009-09-15
申请人： Xuhao Huang , Xiaohong Quan
发明人： Xuhao Huang , Xiaohong Quan
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/13 , H03K5/133 , H03K5/1565 , H03K2005/00136
摘要： A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.
摘要翻译：延迟锁定环（DLL）使用延迟线将第一信号延迟“延迟时间”，从而产生第二信号。电容器以从第一信号的第一边缘开始的第一速率充电并持续到第二信号的边沿。然后电容器以第二速率放电，直到第一信号的另一个边沿。控制回路控制延迟时间，使得电容器的充电量与电容器放电量相同。延迟时间是恒定的并且基本上与第一信号的占空比的变化无关。在一个示例中，通过相对于第一信号占空比的变化按比例改变第一速率来实现占空比失真消除。在另一示例中，第一和第二速率与第一信号的占空比无关。

7. 发明授权

US08564346B2 Non-overlapping clock generation 有权
标题翻译：非重叠时钟产生
公开(公告)号：US08564346B2
公开(公告)日：2013-10-22
申请号：US13356187
申请日：2012-01-23
申请人： Xiaohong Quan , Tongyu Song , Lennart Mathe , Dinesh J. Alladi
发明人： Xiaohong Quan , Tongyu Song , Lennart Mathe , Dinesh J. Alladi
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/1515 , H03K5/1565 , H03K2005/00039 , H03K2005/00097 , H03K2005/00286 , H03M1/12
摘要： Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).
摘要翻译：提供了用于在所需频率范围内产生精确的非重叠时间和时钟相位延迟时间的技术。不重叠的时钟产生电路包括延迟锁定环（DLL）电路，其产生与其耦合的时钟发生器电路的控制电压。控制电压操作以保持由时钟发生器电路产生的不重叠的延迟时钟信号的精确定时关系。在一个方面，DLL电路接收具有已知占空比的输入时钟，并且导出输出控制电压以将单位延迟固定到输入时钟周期的某一部分。时钟发生器电路还可以包括电压控制的延迟单元，其产生彼此延迟非重叠时间（tnlp）的时钟信号组。

8. 发明授权

US08169243B2 Techniques for non-overlapping clock generation 有权
标题翻译：非重叠时钟生成技术
公开(公告)号：US08169243B2
公开(公告)日：2012-05-01
申请号：US12417497
申请日：2009-04-02
申请人： Xiaohong Quan , Tongyu Song , Lennart Mathe , Dinesh J. Alladi
发明人： Xiaohong Quan , Tongyu Song , Lennart Mathe , Dinesh J. Alladi
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/1515 , H03K5/1565 , H03K2005/00039 , H03K2005/00097 , H03K2005/00286 , H03M1/12
摘要： Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.
摘要翻译：提供了用于在所需频率范围内产生精确的非重叠时间和时钟相位延迟时间的技术。在一种配置中，设备包括不重叠的时钟产生电路，其包括延迟锁定环（DLL）电路，该延迟锁定环路（DLL）电路又向与其耦合的时钟发生器电路产生控制电压。控制电压操作以保持由时钟发生器电路产生的不重叠的延迟时钟信号的精确定时关系。在一个方面，DLL电路接收具有已知占空比的输入时钟，并且导出输出控制电压以将单位延迟固定到输入时钟周期的某一部分。在另一方面，时钟发生器电路包括耦合到DLL电路的多个电压控制延迟单元，以产生第一组时钟信号和从第一组时钟信号延迟的第二组时钟信号，重叠时间（tnlp），与制造过程变化无关。

9. 发明授权

US08140026B2 All-digital selectable duty cycle generation 有权
标题翻译：全数字可选占空比生成
公开(公告)号：US08140026B2
公开(公告)日：2012-03-20
申请号：US12436288
申请日：2009-05-06
申请人： Xiaohong Quan , Lennart K. Mathe , Liang Dai , Dinesh J. Alladi
发明人： Xiaohong Quan , Lennart K. Mathe , Liang Dai , Dinesh J. Alladi
IPC分类号： H03K7/08 , H03K5/156
CPC分类号： H03K7/08 , H03K5/1565
摘要： All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.
摘要翻译：用于产生具有可选占空比的周期性数字信号的全数字技术。在一个方面，提供了一个计算块，用于计算所选占空比与参考时钟周期与高频振荡周期之间的离散比的积。计算块可以耦合到脉冲宽度发生器，用于产生具有作为高频振荡器周期的整数倍的脉冲宽度的信号。另一方面，脉冲宽度发生器还可以通过对与高频振荡器的环形振荡器示例性实施例的各个反相器级匹配的延迟线的各个反相器级进行抽头来适应高频振荡器周期的混合分数倍。

10. 发明授权

US08111088B2 Level shifter with balanced duty cycle 有权
标题翻译：电平移位器具有平衡占空比
公开(公告)号：US08111088B2
公开(公告)日：2012-02-07
申请号：US12767370
申请日：2010-04-26
申请人： Ankit Srivastava , Xiaohong Quan
发明人： Ankit Srivastava , Xiaohong Quan
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K3/356113 , H03K5/151 , H03K19/00323 , H03K2005/00136
摘要： A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.
摘要翻译：提供电平移位器和方法来平衡信号的占空比。输入电路接收具有两个互补逻辑电平的差分逻辑信号。电平转换平衡电路在逻辑电平的第一到第二过渡期间平衡每个互补逻辑电平的电平转换版本的上升和下降时间以及电平偏移。逻辑元件存储和提供逻辑电平的电平转换版本的输出。电平转换平衡电路可以包括与用于每个输入的转移元件并联的电容器。电容使输入逻辑元件失稳，并使用电容和先前存储在逻辑元件中的电平平衡转换。

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