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1. 发明申请

US20190333892A1 REDUNDANCY SCHEME FOR A 3D STACKED DEVICE 审中-公开
公开(公告)号：US20190333892A1
公开(公告)日：2019-10-31
申请号：US15967109
申请日：2018-04-30
申请人： Xilinx, Inc.
发明人： Brian C. Gaide , Matthew H. Klein
IPC分类号： H01L25/065 , H01L25/00 , H01L21/66 , H01L23/535
摘要： Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

2. 发明授权

US09436562B1 Circuit network with an error detection system for mitigation of error propagation 有权
标题翻译：具有用于减轻误差传播的错误检测系统的电路网络
公开(公告)号：US09436562B1
公开(公告)日：2016-09-06
申请号：US14171488
申请日：2014-02-03
申请人： Xilinx, Inc.
发明人： Matthew H. Klein , Chen W. Tseng
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/1625 , G06F11/1004
摘要： An apparatus relating generally to an error detection system is disclosed. The apparatus includes a first data bus and a second data bus. A first circuit is coupled for communication via the first data bus. A plurality of storage elements are coupled to the first data bus and the second data bus. A second circuit is coupled for communication via the second data bus. The error detection system is coupled to the first data bus and the second data bus. The error detection system is coupled to compare first data on the first data bus with corresponding second data on the second data bus. The error detection system is configured to generate an error signal responsive to mismatch between the first data and the second data.
摘要翻译：公开了一般涉及错误检测系统的装置。该装置包括第一数据总线和第二数据总线。第一电路被耦合用于经由第一数据总线进行通信。多个存储元件耦合到第一数据总线和第二数据总线。第二电路被耦合用于经由第二数据总线进行通信。误差检测系统耦合到第一数据总线和第二数据总线。错误检测系统被耦合以将第一数据总线上的第一数据与第二数据总线上的对应的第二数据进行比较。错误检测系统被配置为响应于第一数据和第二数据之间的不匹配而产生误差信号。

3. 发明授权

US09075930B2 Configurable embedded memory system 有权
标题翻译：可配置的嵌入式内存系统
公开(公告)号：US09075930B2
公开(公告)日：2015-07-07
申请号：US13673892
申请日：2012-11-09
申请人： Xilinx, Inc.
发明人： Subodh Kumar , James M. Simkins , Thomas H. Strader , Matthew H. Klein , James E. Ogden , Uma Durairajan
IPC分类号： G11C7/10 , G06F13/42 , H03K19/177 , G11C16/26
CPC分类号： G06F13/4234 , G11C7/1006 , G11C7/1039 , G11C7/1069 , G11C7/1096 , G11C16/26 , G11C2207/104 , H03K19/17732 , H03K19/1776 , Y02D10/14 , Y02D10/151
摘要： An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.
摘要翻译：公开了一种存储器模块的实施例。该内存模块是可配置的硬宏。该存储器模块的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器。该部分还包括：耦合以从数据输入多路复用器接收输出以存储在其中的存储器，以及耦合以在存储器的读取数据和级联数据之间进行选择的寄存器输入多路复用器。该存储器模块还包括：耦合以接收来自寄存器输入多路复用器的输出的寄存器，耦合以在来自存储器的读取数据和来自寄存器的寄存数据之间进行选择的锁存/寄存器模式多路复用器，以及数据输出多路复用器，级联数据和从锁存/寄存器模式多路复用器输出以提供输出数据。

4. 发明申请

US20140133246A1 CONFIGURABLE EMBEDDED MEMORY SYSTEM 有权
标题翻译：可配置嵌入式存储系统
公开(公告)号：US20140133246A1
公开(公告)日：2014-05-15
申请号：US13673892
申请日：2012-11-09
申请人： Xilinx, Inc.
发明人： Subodh Kumar , James M. Simkins , Thomas H. Strader , Matthew H. Klein , James E. Ogden , Uma Durairajan
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G06F13/4234 , G11C7/1006 , G11C7/1039 , G11C7/1069 , G11C7/1096 , G11C16/26 , G11C2207/104 , H03K19/17732 , H03K19/1776 , Y02D10/14 , Y02D10/151
摘要： An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.
摘要翻译：公开了一种存储器模块的实施例。该内存模块是可配置的硬宏。该存储器模块的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器。该部分还包括：耦合以从数据输入多路复用器接收输出以存储在其中的存储器，以及耦合以在存储器的读取数据和级联数据之间进行选择的寄存器输入多路复用器。该存储器模块还包括：耦合以接收来自寄存器输入多路复用器的输出的寄存器，耦合以在来自存储器的读取数据和来自寄存器的寄存数据之间进行选择的锁存/寄存器模式多路复用器，以及数据输出多路复用器，级联数据和从锁存/寄存器模式多路复用器输出以提供输出数据。

5. 发明授权

US10032682B1 Multi-die wafer-level test and assembly without comprehensive individual die singulation 有权
公开(公告)号：US10032682B1
公开(公告)日：2018-07-24
申请号：US15359280
申请日：2016-11-22
申请人： Xilinx, Inc.
发明人： Matthew H. Klein , Raghunandan Chaware , Glenn O'Rourke
IPC分类号： H01L21/66 , H01L21/78 , H01L21/56 , H01L23/00
摘要： Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

6. 发明授权

US09509640B2 Latency control in a transmitter/receiver buffer 有权
标题翻译：发送/接收缓冲区中的延迟控制
公开(公告)号：US09509640B2
公开(公告)日：2016-11-29
申请号：US14561452
申请日：2014-12-05
申请人： Xilinx, Inc.
发明人： David F. Taylor , Matthew H. Klein , Vincent Vendramini
IPC分类号： H04K1/10 , G11C7/00 , H04L12/861 , H03L7/06 , G06F5/10 , G06F5/06 , H03M9/00 , G06F5/12
CPC分类号： H04L49/90 , G06F5/06 , G06F5/10 , G06F5/12 , G06F2205/126 , H03L7/06 , H03L7/07 , H03M9/00
摘要： In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.
摘要翻译：在缓冲方法中，缓冲器缓冲响应于读和写时钟信号的数据。来自缓冲器的标志信号用于其填充水平。响应于缓冲的数据高于或低于填充水平的设定点，该标志信号被切换。响应于标志信号的切换，写时钟信号的相位被调整为读时钟信号的相位。写时钟信号用于控制缓冲器的延迟。写时钟信号的相位的调整包括：响应于标志信号的切换产生超控信号; 并将读取的时钟信号和超控信号输入到相位调节器，以在操作期间将写时钟信号的相位可控地调节到读时钟信号的相位。

7. 发明申请

US20160164665A1 LATENCY CONTROL IN A TRANSMITTER/RECEIVER BUFFER 有权
标题翻译：发射机/接收机缓存器中的延迟控制
公开(公告)号：US20160164665A1
公开(公告)日：2016-06-09
申请号：US14561452
申请日：2014-12-05
申请人： Xilinx, Inc.
发明人： David F. Taylor , Matthew H. Klein , Vincent Vendramini
IPC分类号： H04L7/033 , H03L7/06 , H04L12/861 , H03H11/20
CPC分类号： H04L49/90 , G06F5/06 , G06F5/10 , G06F5/12 , G06F2205/126 , H03L7/06 , H03L7/07 , H03M9/00
摘要： In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.
摘要翻译：在缓冲方法中，缓冲器缓冲响应于读和写时钟信号的数据。来自缓冲器的标志信号用于其填充水平。响应于缓冲的数据高于或低于填充水平的设定点，该标志信号被切换。响应于标志信号的切换，写时钟信号的相位被调整为读时钟信号的相位。写时钟信号用于控制缓冲器的延迟。写时钟信号的相位的调整包括：响应于标志信号的切换产生超控信号; 并将读取的时钟信号和超控信号输入到相位调节器，以在操作期间将写时钟信号的相位可控地调节到读时钟信号的相位。

8. 发明授权

US09012245B1 Methods of making integrated circuit products 有权
标题翻译：制作集成电路产品的方法
公开(公告)号：US09012245B1
公开(公告)日：2015-04-21
申请号：US14493078
申请日：2014-09-22
申请人： Xilinx, Inc.
发明人： Matthew H. Klein , Robert W. Wells , Jongheon Jeong
IPC分类号： H01L21/44 , H01L21/66
CPC分类号： H01L22/20 , H01L22/14 , H01L22/22 , H01L2224/16145 , H01L2224/16225 , H01L2924/14 , H01L2924/1431 , H01L2924/14335 , H01L2924/15311
摘要： In the disclosed methods, integrated circuit (IC) dice are manufactured from a common specification, and the IC dice are tested for defective circuitry. Respective defect sets are generated to indicate defective circuitry in the IC die. The dice are assigned to bins based on the respective defect sets. For each bin, all IC dice assigned to the bin have equivalent respective defect sets. Product definitions are provided, and each product definition indicates a respective set of circuitry required for a corresponding product. Respective sets of packages are manufactured for each product. In the manufacturing of each package of a respective set of packages for each product, one or more IC dice are selected from a subset of the plurality of bins such that the IC dice have respective defect sets allowed by the product definition of the product. The selected IC dice are then manufactured into the package.
摘要翻译：在所公开的方法中，集成电路（IC）芯片由公共规范制造，IC芯片被测试有缺陷的电路。产生各个缺陷组以指示IC芯片中的有缺陷的电路。基于相应的缺陷集，将骰子分配给箱子。对于每个仓，分配给仓的所有IC骰子都具有相应的各自的缺陷集。提供了产品定义，每个产品定义都表示相应产品所需的相应电路组。为每个产品制造各套包装。在针对每个产品的相应的一组包装的每个包装的制造中，从多个箱的子集中选择一个或多个IC骰子，使得IC骰子具有由产品的产品定义允许的各自的缺陷组。然后将选定的IC芯片制造成封装。

9. 发明申请

US20140312483A1 SEMICONDUCTOR PACKAGE HAVING IC DICE AND VOLTAGE TUNERS 有权
标题翻译：具有IC数字和电压调谐器的半导体封装
公开(公告)号：US20140312483A1
公开(公告)日：2014-10-23
申请号：US13866893
申请日：2013-04-19
申请人： Xilinx, Inc.
发明人： Thao H.T. Vo , Andy H. Gan , Xiao-Yu Li , Matthew H. Klein
IPC分类号： H01L25/065
CPC分类号： H01L25/0652 , G06F1/3203 , G06F1/324 , G06F17/5045 , G06F17/5054 , H01L25/0655 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/48227 , H01L2224/73257 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2224/05552
摘要： A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.
摘要翻译：半导体封装包括插入件和多个集成电路（IC）芯片，其经由插入器设置并耦合。第一个IC芯片的时钟速度等级大于另一个IC芯片的时钟速度等级。多个可编程电压调谐器分别耦合到多个IC芯片。第一电压调谐器耦合到第一IC芯片，并且第一电压调谐器被编程以降低输入到第一电压调谐器的电压的电压电平，并将降低的电压输出到第一IC芯片。

10. 发明授权

US08694939B1 Method for determining critical junction temperature 有权
标题翻译：确定关键结温的方法
公开(公告)号：US08694939B1
公开(公告)日：2014-04-08
申请号：US13802181
申请日：2013-03-13
申请人： Xilinx, Inc.
发明人： Alan M. Frost , Matthew H. Klein , Ronald L. Cline
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/84
摘要： A method for determining a critical junction temperature for a user-design implemented in a field programmable gate array (programmable device), includes: obtaining a static power vs. temperature curve for the user-design implemented in the programmable device; obtaining a system thermal curve for the user-design implemented in the programmable device; and using the static power vs. temperature curve for the user-design implemented in the programmable device and the system thermal curve for the user-design implemented in the programmable device to determine the critical junction temperature.
摘要翻译：用于确定在现场可编程门阵列（可编程器件）中实现的用户设计的关键结温度的方法包括：获得在可编程器件中实现的用户设计的静态功率对温度曲线; 获得在可编程设备中实现的用户设计的系统热曲线; 并使用在可编程器件中实现的用户设计的静态功率与温度曲线以及在可编程器件中实现的用户设计的系统热曲线来确定临界结温度。

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