专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07989869B2 Non-volatile memory devices having improved operational characteristics 有权
标题翻译：具有改进的操作特性的非易失性存储器件
公开(公告)号：US07989869B2
公开(公告)日：2011-08-02
申请号：US11613345
申请日：2006-12-20
申请人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
发明人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/66833 , H01L29/792
摘要： Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.
摘要翻译：提供非易失性存储器件。器件包括可由形成在半导体衬底上并沿第一方向延伸的器件隔离层限定的有源区。设备还可以包括字线，其可以跨越有效区域并且沿与第一方向相交的第二方向延伸。有源区具有第一间距，并且字线具有大于第一间距的第二间距。

2. 发明申请

US20140061772A1 NON-VOLATILE MEMORY DEVICES HAVING CHARGE STORAGE LAYERS AT INTERSECTING LOCATIONS OF WORD LINES AND ACTIVE REGION 审中-公开
标题翻译：具有充电储存层的非易失性存储器件在字线和主动区域的交替位置
公开(公告)号：US20140061772A1
公开(公告)日：2014-03-06
申请号：US14076806
申请日：2013-11-11
申请人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
发明人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/66833 , H01L29/792
摘要： Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.
摘要翻译：提供非易失性存储器件。器件包括可以由形成在半导体衬底上并沿第一方向延伸的器件隔离层限定的有源区。设备还可以包括字线，其可以跨越有效区域并且沿与第一方向相交的第二方向延伸。有源区具有第一间距，并且字线具有大于第一间距的第二间距。

3. 发明授权

US08610192B2 Non-volatile memory devices having charge storage layers at intersecting locations of word lines and active regions 有权
标题翻译：在字线和有源区域的相交位置处具有电荷存储层的非易失性存储器件
公开(公告)号：US08610192B2
公开(公告)日：2013-12-17
申请号：US13173759
申请日：2011-06-30
申请人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
发明人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory device can include a plurality of parallel active regions that are defined by a plurality of device isolation layers formed on a semiconductor substrate, where each of the plurality of parallel active regions extends in a first direction and has a top surface and sidewalls. A plurality of parallel word lines can extend in a second direction and cross over the plurality of parallel active regions at intersecting locations. A plurality of charge storage layers can be disposed at the intersecting locations between the plurality of parallel active regions and the plurality of parallel word lines. Each of the plurality of charge storage layers at the intersecting locations can have a first side and a second side that is parallel to the second direction and can have a first length, a third side and a fourth side that are parallel to the first direction and can have a second length, where the first length is less than the second length.
摘要翻译：非易失性存储器件可以包括由形成在半导体衬底上的多个器件隔离层限定的多个平行有源区，其中多个平行有源区中的每一个在第一方向上延伸并且具有顶表面和侧壁多个平行字线可以在第二方向上延伸并且在交叉位置处跨越多个平行的有效区域。多个电荷存储层可以设置在多个平行有源区和多个平行字线之间的交叉位置处。在交叉位置处的多个电荷存储层中的每一个可以具有平行于第二方向的第一侧和第二侧，并且可以具有平行于第一方向的第一长度，第三侧和第四侧，可以具有第二长度，其中第一长度小于第二长度。

4. 发明申请

US20070228445A1 NON-VOLATILE MEMORY DEVICES 有权
标题翻译：非易失性存储器件
公开(公告)号：US20070228445A1
公开(公告)日：2007-10-04
申请号：US11613345
申请日：2006-12-20
申请人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
发明人： Won-Cheol Jeong , Su-Jin Ahn , Yoon-Moon Park
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/66833 , H01L29/792
摘要： Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.
摘要翻译：提供非易失性存储器件。器件包括可由形成在半导体衬底上并沿第一方向延伸的器件隔离层限定的有源区。设备还可以包括字线，其可以跨越有效区域并且沿与第一方向相交的第二方向延伸。有源区具有第一间距，并且字线具有大于第一间距的第二间距。

5. 发明申请

US20070133270A1 Phase-change random access memory device and method of operating the same 有权
标题翻译：相变随机存取存储器件及其操作方法
公开(公告)号：US20070133270A1
公开(公告)日：2007-06-14
申请号：US11515422
申请日：2006-09-05
申请人： Chang Jeong , Su-Youn Lee , Won-Cheol Jeong , Jae-Hyun Park , Su-Jin Ahn , Fai Yeung
发明人： Chang Jeong , Su-Youn Lee , Won-Cheol Jeong , Jae-Hyun Park , Su-Jin Ahn , Fai Yeung
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/79
摘要： A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second electrode structure includes a plurality of resistor patterns connected to the phase-change pattern in parallel.
摘要翻译：相变随机存取存储器件可以包括相变图案，连接到相变图案的第一电极结构和与第一电极结构间隔开并连接到相变图案的第二电极结构，其中第一电极结构和第二电极结构中的至少一个包括并联连接到相变图案的多个电阻图案。

6. 发明授权

US07440308B2 Phase-change random access memory device and method of operating the same 有权
标题翻译：相变随机存取存储器件及其操作方法
公开(公告)号：US07440308B2
公开(公告)日：2008-10-21
申请号：US11515422
申请日：2006-09-05
申请人： Chang Wook Jeong , Su-Youn Lee , Won-Cheol Jeong , Jae-Hyun Park , Su-Jin Ahn , Fai Yeung
发明人： Chang Wook Jeong , Su-Youn Lee , Won-Cheol Jeong , Jae-Hyun Park , Su-Jin Ahn , Fai Yeung
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/79
摘要： A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second electrode structure includes a plurality of resistor patterns connected to the phase-change pattern in parallel.
摘要翻译：相变随机存取存储器件可以包括相变图案，连接到相变图案的第一电极结构和与第一电极结构间隔开并连接到相变图案的第二电极结构，其中第一电极结构和第二电极结构中的至少一个包括并联连接到相变图案的多个电阻图案。

7. 发明授权

US08120005B2 Phase change memory devices and their methods of fabrication 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US08120005B2
公开(公告)日：2012-02-21
申请号：US12544104
申请日：2009-08-19
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1666
摘要： In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.
摘要翻译：在一个实施例中，相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的第一层间绝缘层。一个孔穿透第一层间绝缘层。第一和第二半导体图案顺序地堆叠在孔的下部区域中。电池电极设置在第二半导体图案上。电池电极具有比第一层间绝缘层的顶表面更低的表面。限制的相变材料图案填充电池电极上的孔。上电极设置在相变材料图案上。孔中的相变材料图案通过孔与第一和第二半导体图案自对准。还提供了制造相变存储器件的方法。

8. 发明授权

US07671395B2 Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other 失效
标题翻译：具有单元二极管和底部电极彼此自对准的相变存储单元
公开(公告)号：US07671395B2
公开(公告)日：2010-03-02
申请号：US12240267
申请日：2008-09-29
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L27/108
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.
摘要翻译：在其中提供具有垂直二极管的集成电路器件。这些器件包括集成电路衬底和集成电路衬底上的绝缘层。接触孔穿透绝缘层。垂直二极管位于接触孔的下部区域中，接触孔中的底部电极在垂直二极管的顶面具有底面。底部电极与垂直二极管自对准。底部电极的顶表面积小于接触孔的水平截面面积。还提供了形成集成电路器件和相变存储器单元的方法。

9. 发明授权

US07577016B2 Twin-cell semiconductor memory devices 有权
标题翻译：双电池半导体存储器件
公开(公告)号：US07577016B2
公开(公告)日：2009-08-18
申请号：US11094948
申请日：2005-03-31
申请人： Won-Cheol Jeong , Jae-Hyun Park
发明人： Won-Cheol Jeong , Jae-Hyun Park
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1659 , G11C11/1673
摘要： Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers.
摘要翻译：提供了包括多个主位线和多个参考位线的双电池型半导体存储器件。每个参考位线对应于主位线中的相应位线以形成多个位线对。提供多个读出放大器，其电连接到多个位线对中的相应一个。多个主位线或多个参考位线中的至少一个被插入在每个位线对的主位线和对应的参考位线之间。至少一些主位线可以在包含多个读出放大器的半导体存储器件的读出放大器区域中交叉相应的参考位线。

10. 发明申请

US20090026439A1 Phase Change Memory Cells Having a Cell Diode and a Bottom Electrode Self-Aligned with Each Other 失效
标题翻译：具有电池二极管和底部电极的相变存储器单元彼此自对准
公开(公告)号：US20090026439A1
公开(公告)日：2009-01-29
申请号：US12240267
申请日：2008-09-29
申请人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
发明人： Jae-Hyun Park , Jae-Hee Oh , Se-Ho Lee , Won-Cheol Jeong
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.
摘要翻译：在其中提供具有垂直二极管的集成电路器件。这些器件包括集成电路衬底和集成电路衬底上的绝缘层。接触孔穿透绝缘层。垂直二极管位于接触孔的下部区域中，接触孔中的底部电极在垂直二极管的顶面具有底面。底部电极与垂直二极管自对准。底部电极的顶表面积小于接触孔的水平截面面积。还提供了形成集成电路器件和相变存储器单元的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式