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1. 发明授权

US5008568A CMOS output driver 失效
标题翻译： CMOS输出驱动
公开(公告)号：US5008568A
公开(公告)日：1991-04-16
申请号：US565169
申请日：1990-08-08
申请人： Wingyu Leung , Chuen-Der Lien
发明人： Wingyu Leung , Chuen-Der Lien
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/0185 , H03K19/00361
摘要： A transistor configured as a capacitor is connected between the gate and drain of an output, pull-down transistor to limit the rate of change (di/dt) of the current conducted through the pull-down transistor during the turn-on of the transistor to limit ground bounce (transients). Drive for the pull-down transistor is provided, in part, by a NOR gate, the transistors of which are sized to provide a finite resistive to the pull-down transistor. Additional drive for the pull-down transistor is provided by a transistor connected to function as a resistive pull-up between the gate and the drain of the pull-down transistor.
摘要翻译：配置为电容器的晶体管连接在输出下拉晶体管的栅极和漏极之间，以限制晶体管导通期间通过下拉晶体管传导的电流的变化率（di / dt）限制地面反弹（瞬变）。用于下拉晶体管的驱动部分地由或非门提供，其中晶体管的尺寸被设计成提供对下拉晶体管的有限电阻。下拉晶体管的附加驱动器由连接到下拉晶体管的栅极和漏极之间的电阻上拉的晶体管提供。

2. 发明授权

US4933574A BiCMOS output driver 失效
标题翻译： BiCMOS输出驱动
公开(公告)号：US4933574A
公开(公告)日：1990-06-12
申请号：US303855
申请日：1989-01-30
申请人： Chuen-Der Lien , Wingyu Leung
发明人： Chuen-Der Lien , Wingyu Leung
IPC分类号： H03K17/16 , H03K17/687 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/01721 , H03K19/00361 , H03K19/09448
摘要： A bipolar transistor and two field-effect transistors are connected in a BiCMOS pull-down configuration to pull-down to a (first) predetermined potential level the potential developed on an output line when a high logic level potential is developed on an input line. To maximize switching speed and to minimize ground bounce (transients), the bipolar transistor is not permitted to go into saturation. A pair of transistors, connected in an inverter configuration, develop a signal which indicates when the bipolar transistor pulls-down the level of the potential on the output line below a (second) predetermined potential level. From a signal developed from the input line signal and a signal developed from the inverter developed signal, a gate develops a signal which drives a transistor that pulls-down from the (first) predetermined potential level to a low logic level potential the output line potential three gate delay times after the output line potential level falls below the (second) predetermined potential level.

3. 发明授权

US08228726B2 N-channel SONOS non-volatile memory for embedded in logic 有权
标题翻译：用于嵌入逻辑的N沟道SONOS非易失性存储器
公开(公告)号：US08228726B2
公开(公告)日：2012-07-24
申请号：US12906153
申请日：2010-10-18
申请人： Gang-Feng Fang , Wingyu Leung
发明人： Gang-Feng Fang , Wingyu Leung
IPC分类号： G11C16/04 , H01L29/788 , H01L21/336
CPC分类号： H01L27/11565 , G11C16/0466 , G11C16/28 , H01L27/11568 , H01L27/11573
摘要： A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.
摘要翻译：公开了一种通过添加ONO沉积和蚀刻的单一多逻辑工艺制造的电可编程和可擦除非易失性存储单元的系统和方法。在一个实施例中，非易失性存储器系统包括至少一个非易失性存储器单元，其由在P衬底上制造的SONOS晶体管构成，其中深N阱位于P衬底中，P阱位于深N井存储单元还包括一个访问NMOS晶体管，其耦合到SONOS晶体管并且位于包括仅氧化物栅电介质的相同P阱中。电池可以用其他晶体管的修改逻辑工艺制造，并保留其物理特性。

4. 发明授权

US07353438B2 Transparent error correcting memory 失效
标题翻译：透明错误纠正内存
公开(公告)号：US07353438B2
公开(公告)日：2008-04-01
申请号：US10645861
申请日：2003-08-20
申请人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
发明人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.
摘要翻译：具有透明误差校正电路的存储器系统为测试数据模式和相应的纠错码（ECC）值提供完全卡住的故障覆盖。存储器系统包括具有存储器阵列，存储器接口和错误检测/校正单元的半导体存储器。存储器阵列被配置为存储测试数据模式和相应的纠错码（ECC）值。存储器接口被配置为使得ECC值不能直接访问。错误检测/校正单元被配置为校正测试数据模式中的单位错误和对应的ECC值。选择与半导体存储器相关联的一组测试数据模式，使得测试数据模式中的任何多位错误和相应的ECC值导致错误检测/校正单元提供具有错误的输出数据模式，从而渲染多个位错误100％可检测。

5. 发明授权

US07274618B2 Word line driver for DRAM embedded in a logic process 有权
标题翻译：用于嵌入在逻辑过程中的DRAM的字线驱动器
公开(公告)号：US07274618B2
公开(公告)日：2007-09-25
申请号：US11166856
申请日：2005-06-24
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C8/00 , G11C5/14 , G11C7/00 , G11C5/06 , G11C11/34
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/104 , H01L27/10897
摘要： A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.
摘要翻译：提供了用于访问嵌入在常规逻辑处理中的DRAM单元的字线驱动器。 DRAM单元包括耦合到单元电容器的p沟道存取晶体管。字线驱动器包括位于p阱中的n沟道晶体管，其中p阱位于深n阱中。深n阱位于p型衬底中。字线将n沟道晶体管的漏极耦合到p沟道存取晶体管的栅极。负升压电压对p沟道和n沟道晶体管的源极施加负升压电压。负升压电压小于接地，等于或大于p沟道存取晶体管的阈值电压。深n阱和p型衬底耦合到地面。在另一个实施例中，各种极性可以颠倒。

6. 发明申请

US20070170489A1 Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process 审中-公开
标题翻译：增加在单门逻辑过程中制造的非易失性存储器的电荷保留的方法
公开(公告)号：US20070170489A1
公开(公告)日：2007-07-26
申请号：US11341881
申请日：2006-01-26
申请人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
发明人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/42324
摘要： A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.
摘要翻译：具有增加的电荷保持的非易失性存储单元使用单栅极常规逻辑工艺在与逻辑器件相同的衬底上制造。在NVM单元的浮动栅极上形成硅化物阻挡介质结构，从而防止在浮栅上形成硅化物，同时允许在逻辑器件上形成硅化物。在NVM电池中防止硅化物尖峰和桥接，因为硅化物阻挡电介质结构防止硅化物金属与浮动栅极或相邻的侧壁间隔物接触。硅化物阻挡电介质层可以暴露NVM电池的有源区的部分，远离浮动栅极和相邻的侧壁间隔物，从而使得这些部分上形成硅化物。或者，硅化物阻挡电介质层可以在硅化物形成期间覆盖NVM电池的有源区。在这种情况下，硅化物阻挡介电层可以在形成硅化物之后变薄或去除。

7. 发明授权

US07206913B2 High speed memory system 有权
标题翻译：高速存储系统
公开(公告)号：US07206913B2
公开(公告)日：2007-04-17
申请号：US10927157
申请日：2004-08-25
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线以及包括与CPU总线耦合的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

8. 发明申请

US20060123322A1 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory 有权
标题翻译：在半导体存储器中促进高速字节写入的预测性纠错码产生
公开(公告)号：US20060123322A1
公开(公告)日：2006-06-08
申请号：US10997604
申请日：2004-11-23
申请人： Wingyu Leung , Kit Tam
发明人： Wingyu Leung , Kit Tam
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.
摘要翻译：以实现错误代码校正的存储器系统中的部分字写入事务的预测方式生成写校验位。从存储器的地址读取读取数据字和相关联的读取校验位。如果读取数据字的一个字节存在错误，则识别该字节。同时，未校正的读取数据字的一个或多个字节与写入数据字的一个或多个字节合并，从而创建合并的数据字。响应于合并的数据字生成写校验位。如果合并的数据字包含包含错误的读取数据字的字节，则修改校验位以反映该错误。合并的数据字和修改的（或未修改的）写入校验位然后被写入存储器的地址。

9. 发明授权

US06898140B2 Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors 有权
标题翻译：使用MOSFET晶体管的亚阈值特性的1T-SRAM兼容存储器中的温度自适应刷新方法和装置
公开(公告)号：US06898140B2
公开(公告)日：2005-05-24
申请号：US10300427
申请日：2002-11-20
申请人： Wingyu Leung , Jae-Kwang Sim
发明人： Wingyu Leung , Jae-Kwang Sim
IPC分类号： A61B17/34 , A61J15/00 , G11C7/22 , G11C11/00 , G11C11/406 , G11C7/00
CPC分类号： G11C11/406 , G11C7/22 , G11C11/005 , G11C11/40618 , G11C11/40626
摘要： A memory system is provided that includes an array of memory cells that require periodic refresh, and a temperature-adaptive refresh controller. Data retention time of the memory cells decreases exponentially as temperature increases. The temperature-adaptive refresh controller selects the refresh period of the memory cells in response to the subthreshold current of a reference transistor. The subthreshold current of the reference transistor increases exponentially as temperature increases As a result, the refresh period is empirically tied to the data retention time. Consequently, the power required for refresh operations decreases as temperature decreases. Power is therefore conserved in applications that operate predominantly at room temperature.
摘要翻译：提供了一种存储系统，其包括需要周期性刷新的存储器单元阵列和温度自适应刷新控制器。随着温度的升高，存储单元的数据保留时间呈指数下降。温度自适应刷新控制器响应于参考晶体管的亚阈值电流来选择存储器单元的刷新周期。参考晶体管的亚阈值电流随着温度升高而呈指数增长。结果，刷新周期与经历数据保留时间相关。因此，刷新操作所需的功率随着温度的降低而降低。因此，在主要在室温下工作的应用中，功率是保守的。

10. 发明申请

US20050027929A1 High speed memory system 有权
标题翻译：高速存储系统
公开(公告)号：US20050027929A1
公开(公告)日：2005-02-03
申请号：US10927157
申请日：2004-08-25
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线以及包括与CPU总线耦合的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加了DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

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