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1. 发明授权

US08175143B1 Adaptive equalization using data level detection 有权
标题翻译：使用数据级检测的自适应均衡
公开(公告)号：US08175143B1
公开(公告)日：2012-05-08
申请号：US12037284
申请日：2008-02-26
申请人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
发明人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03356 , H04L2025/03745 , H04L2025/03783
摘要： A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.
摘要翻译：用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机以提取用于数字化的参考电平并控制均衡曲线。参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。状态机优选是可编程的。这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

2. 发明授权

US08208523B2 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US08208523B2
公开(公告)日：2012-06-26
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

3. 发明申请

US20110188564A1 DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：数字适配电路和可编程逻辑器件的方法
公开(公告)号：US20110188564A1
公开(公告)日：2011-08-04
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03K5/125 , H03K5/19
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

4. 发明授权

US07514968B1 H-tree driver circuitry 有权
标题翻译： H树驱动电路
公开(公告)号：US07514968B1
公开(公告)日：2009-04-07
申请号：US11786295
申请日：2007-04-10
申请人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
发明人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Tim Tri Hoang
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272
摘要： An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.
摘要翻译： H-tree驱动电路具有上拉和下拉电流源，每个都使用低压共源共栅拓扑来实现。

5. 发明授权

US07920621B2 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US07920621B2
公开(公告)日：2011-04-05
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

6. 发明申请

US20080069276A1 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US20080069276A1
公开(公告)日：2008-03-20
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H04B1/10
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

7. 发明申请

US20110188621A1 CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES 有权
标题翻译：时钟和数据恢复电路与自动调速和其他可能的特性
公开(公告)号：US20110188621A1
公开(公告)日：2011-08-04
申请号：US12700433
申请日：2010-02-04
申请人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
IPC分类号： H04L7/00
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。这可以帮助IC支持采用自动速度协商的通信协议。

8. 发明授权

US08811555B2 Clock and data recovery circuitry with auto-speed negotiation and other possible features 有权
标题翻译：时钟和数据恢复电路，具有自动速度协商和其他可能的功能
公开(公告)号：US08811555B2
公开(公告)日：2014-08-19
申请号：US12700433
申请日：2010-02-04
申请人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
IPC分类号： H04L7/00 , H03L7/081 , H04L7/033 , H03L7/08
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。

9. 发明授权

US08208528B1 Programmable adaptation convergence detection 有权
标题翻译：可编程自适应收敛检测
公开(公告)号：US08208528B1
公开(公告)日：2012-06-26
申请号：US11955948
申请日：2007-12-13
申请人： Tin H. Lai , Sergey Shumarayev , Tim Tri Hoang
发明人： Tin H. Lai , Sergey Shumarayev , Tim Tri Hoang
IPC分类号： H03H7/30
CPC分类号： H04B10/695
摘要： Adaptation convergence in an adaptive dispersion compensation engine (ADCE) of a high-speed serial interface is detected by monitoring the output of the error amplifier of one or more adjustment loops of the ADCE. Adaptation convergence is considered to have been detected upon detection of a predetermined number of transitions in the error amplifier output, each of which occurs within a preselected interval following the previous transition. The detector may be implemented with a timer that times the preselected interval and a counter that counts transitions in the error amplifier output. The timer restarts each time a transition occurs, and the counter outputs a convergence signal when it reaches the predetermined number, but is reset each time the timer reaches the preselected interval. The serial interface may be part of a programmable integrated circuit device and in any case the preselected interval and the predetermined number may be programmable.
摘要翻译：通过监视ADCE的一个或多个调节回路的误差放大器的输出来检测高速串行接口的自适应色散补偿引擎（ADCE）中的适应收敛。认为在误差放大器输出中检测到预定数量的转换后已经检测到适应收敛，其中每一个都在先前转换之后的预选间隔内发生。检测器可以用定时器实现，该定时器乘以预选间隔，而计数器可以对误差放大器输出中的转换进行计数。定时器在每次转换发生时重新开始计时，当计数器达到预定数量时，计数器输出会聚信号，但每当定时器达到预先选定的时间间隔时，计数器都会被复位。串行接口可以是可编程集成电路器件的一部分，并且在任何情况下，预选间隔和预定数量可以是可编程的。

10. 发明授权

US08063807B1 Equalization circuitry including a digital-to-analog converter having a voltage divider and a multiplexer 有权
标题翻译：均衡电路包括具有分压器和多路复用器的数模转换器
公开(公告)号：US08063807B1
公开(公告)日：2011-11-22
申请号：US12433310
申请日：2009-04-30
申请人： Tin H. Lai , Sergey Shumarayev , Tim Tri Hoang
发明人： Tin H. Lai , Sergey Shumarayev , Tim Tri Hoang
IPC分类号： H03M1/06
CPC分类号： H04L25/03019 , H03G5/165 , H04L25/03885
摘要： An equalization circuitry that includes a digital-to-analog converter having a voltage divider and a multiplexer coupled to the voltage divider is described. In one implementation, the digital-to-analog converter provides a control signal to a plurality of single-stage equalizer control logic circuits. Also, in one implementation, the multiplexer receives a plurality of inputs from the voltage divider and selects an output from the plurality of inputs. Furthermore, in one implementation, the voltage divider includes a plurality of resistors coupled in series. Also, in one implementation, the voltage divider further includes a first resistor coupled to the plurality of resistors, ground, and a lowest voltage input terminal of the multiplexer, where a voltage across the first resistor is an input voltage to the lowest voltage input terminal. Additionally, in one implementation, the voltage divider further includes a second resistor coupled to the plurality of resistors and a supply voltage, where the supply voltage minus a voltage across the second resistor and a voltage across a resistor of the plurality of resistors is an input voltage to a highest voltage input terminal of the multiplexer. In one implementation, the first and second resistors are programmable in user mode.
摘要翻译：描述了包括具有分压器和耦合到分压器的多路复用器的数模转换器的均衡电路。在一个实现中，数模转换器向多个单级均衡器控制逻辑电路提供控制信号。而且，在一个实现中，多路复用器从分压器接收多个输入并选择多个输入的输出。此外，在一个实施方式中，分压器包括串联耦合的多个电阻器。此外，在一个实施方式中，分压器还包括耦合到多个电阻器的接地的第一电阻器和多路复用器的最低电压输入端子，其中第一电阻器两端的电压是输入电压到最低电压输入端子。此外，在一个实施方式中，分压器还包括耦合到多个电阻器的第二电阻器和电源电压，其中电源电压减去第二电阻器两端的电压和多个电阻器两端的电阻器两端的电压是输入电压到多路复用器的最高电压输入端。在一个实现中，第一和第二电阻器在用户模式下是可编程的。

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