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1. 发明申请

US20050231236A1 Routing architecture with high speed I/O bypass path 有权
标题翻译：具有高速I / O旁路路径的路由架构
公开(公告)号：US20050231236A1
公开(公告)日：2005-10-20
申请号：US10825387
申请日：2004-04-14
申请人： William Vest , Paul Leventis
发明人： William Vest , Paul Leventis
IPC分类号： H03K19/177
CPC分类号： H03K19/17792 , H03K19/17736 , H03K19/17744
摘要： Improved routing architectures including one or more high speed input/output (I/O) bypass paths are provided for use in, for example, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). The output bypass paths add additional routing connections to the routing architecture, providing faster connections between the output of a logic element (LE) in the PLD and external circuitry. In one embodiment, an output bypass path is used for directly connecting the output of the LE to the input of an I/O multiplexer of an I/O block. In another embodiment, the output bypass path also bypasses the I/O multiplexer, providing a direct connection between the output of the LE and a bypass multiplexer of the I/O block. Also provided is an input bypass path which provides direct connections between an input buffer of the I/O block and an otherwise dangling conductor at the periphery of the PLD's routing architecture.
摘要翻译：提供了改进的路由架构，包括一个或多个高速输入/输出（I / O）旁路路径，用于例如可编程逻辑器件（PLD），例如现场可编程门阵列（FPGA）。输出旁路路径为路由架构添加了额外的路由连接，从而在PLD中的逻辑元件（LE）的输出与外部电路之间提供更快的连接。在一个实施例中，输出旁路路径用于将LE的输出直接连接到I / O块的I / O多路复用器的输入端。在另一个实施例中，输出旁路路径也绕过I / O多路复用器，提供LE的输出和I / O块的旁路多路复用器之间的直接连接。还提供了一种输入旁路路径，其提供I / O块的输入缓冲器与PLD路由架构外围的另一悬挂导体之间的直接连接。

2. 发明授权

US07656191B2 Distributed memory in field-programmable gate array integrated circuit devices 有权
标题翻译：现场可编程门阵列集成电路器件中的分布式存储器
公开(公告)号：US07656191B2
公开(公告)日：2010-02-02
申请号：US12156403
申请日：2008-05-30
申请人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
发明人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
IPC分类号： H03K19/177
CPC分类号： G11C7/1045 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.
摘要翻译：用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

3. 发明授权

US07644386B1 Redundancy structures and methods in a programmable logic device 失效
标题翻译：可编程逻辑器件中的冗余结构和方法
公开(公告)号：US07644386B1
公开(公告)日：2010-01-05
申请号：US11623903
申请日：2007-01-17
申请人： Michael Chan , Paul Leventis , David Lewis , Ketan Zaveri , Hyun Mo Yi , Chris Lane
发明人： Michael Chan , Paul Leventis , David Lewis , Ketan Zaveri , Hyun Mo Yi , Chris Lane
IPC分类号： G06F17/50
CPC分类号： H03K19/17764 , H03K19/17736
摘要： An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
摘要翻译：本发明的实施例提供了一种可编程逻辑器件（“PLD”），其包括适于经由第一或第二交错垂直线选择性路由信号的冗余架构。其他实施例提供用于确定路由选择的配置逻辑和程序。其他实施例提供从相同行驱动的垂直线的近似分组。其他实施例提供了一旦有缺陷的行位置是已知的备用行位置的定义。

4. 发明申请

US20080231316A1 Distributed memory in field-programmable gate array integrated circuit devices 有权
标题翻译：现场可编程门阵列集成电路器件中的分布式存储器
公开(公告)号：US20080231316A1
公开(公告)日：2008-09-25
申请号：US12156403
申请日：2008-05-30
申请人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
发明人： David Lewis , Paul Leventis , Vaughn Betz , Thomas Yau-Tsun Wong , Andy Lee , Philip Pan
IPC分类号： H03K19/177
CPC分类号： G11C7/1045 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.
摘要翻译：用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

5. 发明授权

US07400167B2 Apparatus and methods for optimizing the performance of programmable logic devices 有权
标题翻译：用于优化可编程逻辑器件性能的装置和方法
公开(公告)号：US07400167B2
公开(公告)日：2008-07-15
申请号：US11204570
申请日：2005-08-16
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： H03K19/173
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

6. 发明授权

US07236633B1 Data compression and decompression techniques for programmable circuits 有权
标题翻译：可编程电路的数据压缩和解压缩技术
公开(公告)号：US07236633B1
公开(公告)日：2007-06-26
申请号：US10394472
申请日：2003-03-21
申请人： David Lewis , Paul Leventis
发明人： David Lewis , Paul Leventis
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H03M7/30
摘要： The present invention provides techniques for compressing and decompressing data in a programmable circuit. Programmable circuits can be configured according to user design by configuration data. Configuration data is compressed using a compression algorithm to save memory space. When the configuration data is needed, the compressed configuration data is decompressed using a decompressor. A decompressor can decompress configuration data using a variety of decompression algorithms such as arithmetic decoding. In an arithmetic encoding algorithm, symbol probabilities are used to increase compression of the data. The symbol probabilities can be transferred in a header of the encoded data stream and subsequently stored in a symbol probability table. The input of the decompressor may be coupled to a FIFO that temporarily stores the encoded data until it can be used by the decompressor.
摘要翻译：本发明提供了用于在可编程电路中压缩和解压缩数据的技术。可根据用户设计的配置数据配置可编程电路。使用压缩算法对配置数据进行压缩，以节省内存空间。当需要配置数据时，使用解压缩器对压缩的配置数据进行解压缩。解压缩器可以使用诸如算术解码的各种解压缩算法解压缩配置数据。在算术编码算法中，使用符号概率来增加数据的压缩。符号概率可以在编码数据流的报头中传送并随后存储在符号概率表中。解压缩器的输入可以耦合到临时存储编码数据的FIFO，直到解压缩器可以使用它。

7. 发明申请

US20060033527A1 PLD architecture for flexible placement of IP functions blocks 有权
标题翻译：用于灵活放置IP功能块的PLD架构
公开(公告)号：US20060033527A1
公开(公告)日：2006-02-16
申请号：US11202616
申请日：2005-08-12
申请人： Andy Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Betz , David Lewis
发明人： Andy Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Betz , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译：根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

8. 发明授权

US08694946B1 Simultaneous switching noise optimization 有权
标题翻译：同时开关噪声优化
公开(公告)号：US08694946B1
公开(公告)日：2014-04-08
申请号：US12465452
申请日：2009-05-13
申请人： Joshua David Fender , Navid Azizi , Paul Leventis
发明人： Joshua David Fender , Navid Azizi , Paul Leventis
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/504 , G06F2217/82
摘要： This invention provides methods, computer program products, and systems to guide a user in optimizing the Simultaneous Switching Noise (SSN) of an electronic device by using visual approaches on a graphical user interface (GUI). Also provided is an interactive feedback mechanism that enables the user to evaluate the effectiveness of an optimization method. A matrix representation of the different I/O pins on the device shows the level of SSN at different victim pins caused by switching aggressor pins. The SSN is depicted using different graphical representations. Associated with the SSN of each victim pin is the graphical representation of its accuracy. The accuracy rating denotes the reliability of the SSN and is an indication of how sensitive a victim pin is to errors. In the interactive feedback mechanism, user input on SSN optimization is received and used to calculate the new SSN and accuracy rating of different victim pins on the device. The new data is then updated in a timely manner on the GUI.
摘要翻译：本发明提供了通过使用图形用户界面（GUI）上的可视方法来指导用户优化电子设备的同时切换噪声（SSN）的方法，计算机程序产品和系统。还提供了一种交互式反馈机制，使得用户能够评估优化方法的有效性。设备上不同I / O引脚的矩阵表示显示了由切换引脚引起的不同受扰引脚上的SSN电平。使用不同的图形表示描绘SSN。与每个受害者引脚的SSN相关联的是其精度的图形表示。精度等级表示SSN的可靠性，并且表示受害者引脚对错误的敏感程度。在交互式反馈机制中，接收SSN优化用户输入，用于计算设备上不同受害引脚的新SSN和精度等级。然后在GUI上及时更新新数据。

9. 发明授权

US08443321B1 Pessimism removal in the modeling of simultaneous switching noise 有权
标题翻译：同步开关噪声建模中的悲观消除
公开(公告)号：US08443321B1
公开(公告)日：2013-05-14
申请号：US12137407
申请日：2008-06-11
申请人： Joshua David Fender , Kamal Patel , Navid Azizi , Paul Leventis
发明人： Joshua David Fender , Kamal Patel , Navid Azizi , Paul Leventis
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.
摘要翻译：提出了通过一组侵略者信号确定给定受害者的感应噪声的方法，并且用于识别导致最坏情况的受害者噪声的最坏情况侵权者切换时间对准。该方法通过确定电路设计中的受害者 - 侵入者输入/输出（I / O）引脚的物理不可能组合，并从列表中剔除不可能的组合，从而消除了电路设计工具中与同时开关噪声（SSN）相关的电路分析悲观情绪可能的受害者 - 侵略者组合。该方法还考虑到可能的受害者 - 侵略者组合的列表，执行具有公共不确定性去除算法的电路设计的切换窗口SSN分析，并且确定在电路设计的I / O引脚上引起的最大电压噪声。噪声分析的结果显示给用户。

10. 发明申请

US20090224800A1 PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS 有权
标题翻译：用于柔性布置IP功能块的PLD架构
公开(公告)号：US20090224800A1
公开(公告)日：2009-09-10
申请号：US12465464
申请日：2009-05-13
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译：根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

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