会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Methods and apparatus for constant-weight encoding and decoding
    • 用于恒权重编码和解码的方法和装置
    • US07098817B2
    • 2006-08-29
    • US11036146
    • 2005-01-14
    • William P. CorneliusWilliam C. Athas
    • William P. CorneliusWilliam C. Athas
    • H03M5/00
    • G06F13/4027H03M13/23H03M13/41
    • Methods and apparatus for spreading and concentrating information to constant-weight encode data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.
    • 用于扩展和集中信息以在并行数据线总线上对数据字进行恒权重编码的方法和装置,同时允许跨越子字路径的信息通信。 在一个实施例中,仅通过差分架构获得的数据传输速率仅通过单端架构上的行数小幅增加来实现。 例如,18位数据字需要22个用于传输的编码数据线,其中先前需要16行和32行才能以单端和差分架构传输未编码的数据。 恒定并行编码在并行编码数据线和信号线的高电平和低电位驱动电路中保持恒定电流。
    • 2. 发明授权
    • Methods and apparatus for constant-weight encoding & decoding
    • 用于恒权重编码和解码的方法和装置
    • US06661355B2
    • 2003-12-09
    • US09752508
    • 2000-12-27
    • William P. CorneliusWilliam C. Athas
    • William P. CorneliusWilliam C. Athas
    • H03M500
    • G06F13/4027H03M13/23H03M13/41
    • Methods and apparatus for spreading and concentrating information to constant-weight encode data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.
    • 用于扩展和集中信息以在并行数据线总线上对数据字进行恒权重编码的方法和装置,同时允许跨越子字路径的信息通信。 在一个实施例中,仅通过差分架构获得的数据传输速率仅通过单端架构上的行数小幅增加来实现。 例如,18位数据字需要22个用于传输的编码数据线,其中先前需要16行和32行来传输具有单端和差分架构的未编码数据。 恒定并行编码在并行编码数据线和信号线的高电平和低电位驱动电路中保持恒定电流。
    • 3. 发明授权
    • Methods and apparatus for constant-weight encoding and decoding
    • 用于恒权重编码和解码的方法和装置
    • US06844833B2
    • 2005-01-18
    • US10691344
    • 2003-10-21
    • William P. CorneliusWilliam C. Athas
    • William P. CorneliusWilliam C. Athas
    • G06F5/00H03M7/02H03M13/23H03M13/41H03M5/00
    • G06F13/4027H03M13/23H03M13/41
    • Methods and apparatus for spreading and concentrating information to constant-weight encode of data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.
    • 用于扩展和集中信息以在并行数据线总线上对数据字进行恒权重编码的同时允许跨子字路径进行信息通信的方法和装置。 在一个实施例中,仅通过差分架构获得的数据传输速率仅通过单端架构上的行数小幅增加来实现。 例如,18位数据字需要22个用于传输的编码数据线,其中先前需要16行和32行来传输具有单端和差分架构的未编码数据。 恒定并行编码在并行编码数据线和信号线的高电平和低电位驱动电路中保持恒定电流。
    • 8. 发明授权
    • Controlling power loss in a switched-capacitor power converter
    • 控制开关电容电源转换器的功率损耗
    • US08541999B2
    • 2013-09-24
    • US12783728
    • 2010-05-20
    • William C. AthasThomas C. Greening
    • William C. AthasThomas C. Greening
    • G05F1/00H02M3/18
    • H02M3/07H02M2001/0048Y02B70/1491
    • The disclosed embodiments relate to a system that implements a switched-capacitor power converter which is configured to actively control power loss while converting an input voltage to an output voltage. This system includes one or more switched-capacitor blocks (SCBs), wherein each SCB includes a first capacitor and a set of switching devices configured to couple a constant-potential terminal and a time-varying-potential terminal of the first capacitor between the input voltage, the output voltage and a reference voltage. The system also includes a clocking circuit which produces gate drive signals for switching transistors in the one or more SCBs. The system additionally includes a controller configured to actively control the gate drive signals from the clocking circuit to substantially minimize the power loss for the switched-capacitor power converter.
    • 所公开的实施例涉及实现开关电容器功率转换器的系统,其被配置为在将输入电压转换为输出电压的同时主动地控制功率损耗。 该系统包括一个或多个开关电容器块(SCB),其中每个SCB包括第一电容器和一组开关器件,其被配置为将第一电容器的恒定电位端子和时变电位端子耦合在输入端 电压,输出电压和参考电压。 该系统还包括产生用于在一个或多个SCB中的开关晶体管的栅极驱动信号的时钟电路。 该系统还包括控制器,其被配置为主动地控制来自时钟电路的栅极驱动信号,以基本上最小化开关电容器功率转换器的功率损耗。
    • 9. 发明授权
    • Resonant oscillator circuit with reduced startup transients
    • 谐振振荡电路具有降低的启动瞬变
    • US08085103B2
    • 2011-12-27
    • US12629370
    • 2009-12-02
    • William C. Athas
    • William C. Athas
    • H03K3/282
    • H02M3/07H03B5/06H03B5/1212H03B5/1228H03B2200/0094H03B2200/0096
    • Some embodiments of the present invention provide a system that implements a resonant oscillator circuit. This resonant oscillator circuit includes: a first inductor, a second inductor, a first capacitance, and a second capacitance, wherein the first and second inductors are configured to operate with the first and second capacitances to produce resonant oscillations which appear at a first phase output and a second phase output. The system also includes a startup circuit which is configured to start the resonant oscillator circuit in a state where: the first phase output is at a peak voltage; the second phase output is at a base voltage; and currents through the first and second inductors are substantially zero. By starting the resonant oscillator circuit in this state, the oscillations commence without a significant startup transient.
    • 本发明的一些实施例提供一种实现谐振振荡器电路的系统。 该谐振振荡器电路包括:第一电感器,第二电感器,第一电容器和第二电容器,其中第一和第二电感器被配置为与第一和第二电容器一起工作,以产生出现在第一相位输出 和第二相输出。 该系统还包括启动电路,其被配置为在第一相输出处于峰值电压的状态下启动谐振振荡器电路; 第二相输出为基极电压; 并且通过第一和第二电感器的电流基本上为零。 通过在该状态下启动谐振振荡器电路,振荡开始而没有明显的启动瞬变。
    • 10. 发明授权
    • Resonant oscillator with oscillation-startup circuitry
    • 具有振荡启动电路的谐振振荡器
    • US07982548B2
    • 2011-07-19
    • US12540578
    • 2009-08-13
    • William C. Athas
    • William C. Athas
    • H03B5/12
    • H02M3/07H03B5/06H03B5/1212H03B5/1228H03B2200/0094H03B2200/0096
    • Some embodiments of the present invention provide a system that implements a resonant oscillator circuit. This system includes a first inductor with a constant potential terminal coupled to an input voltage, and a time-varying potential terminal coupled to a first phase output. The system also includes a second inductor with a constant potential terminal coupled to the input voltage, and a time-varying potential terminal coupled to a second phase output. The system additionally includes a first n-type transistor with a source terminal coupled to a base voltage, a drain terminal coupled to the first phase output, and a gate terminal coupled to the second phase output. The system also includes a second n-type transistor with a source terminal coupled to the base voltage, a drain terminal coupled to the second phase output, and a gate terminal coupled to the first phase output. Finally, the system includes a startup circuit configured to commence oscillations in the resonant oscillator circuit by energizing the first inductor before energizing the second inductor.
    • 本发明的一些实施例提供一种实现谐振振荡器电路的系统。 该系统包括具有耦合到输入电压的恒定电位端的第一电感器和耦合到第一相输出的时变电位端子。 该系统还包括具有耦合到输入电压的恒定电位端子的第二电感器和耦合到第二相输出端的时变电位端子。 该系统还包括具有耦合到基极电压的源极端子的第一n型晶体管,耦合到第一相位输出的漏极端子和耦合到第二相位输出的栅极端子。 该系统还包括具有耦合到基极电压的源极端子的第二n型晶体管,耦合到第二相位输出的漏极端子和耦合到第一相位输出的栅极端子。 最后,该系统包括启动电路,该启动电路经配置以在激励第二电感器之前激励第一电感器来开始谐振振荡器电路中的振荡。