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1. 发明授权

US07061117B2 Bump layout on silicon chip 有权
公开(公告)号：US07061117B2
公开(公告)日：2006-06-13
申请号：US10708665
申请日：2004-03-18
申请人： Wen-Chih Yang , Feng-Cheng Su , Chin-Chen Yang
发明人： Wen-Chih Yang , Feng-Cheng Su , Chin-Chen Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/17 , H01L23/50 , H01L2224/13099 , H01L2924/01033 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A bump layout on the active region of a driver IC for increasing overall bump count. The layout fits IC packages that have a narrow and long body profile. Bumps are positioned close to the long side and central regions of the active region so that low marking pressure on the shorter sides of the package during chip-glass bondage is avoided. Dummy bumps may also be positioned close to the shorter sides of the package so that pressure distribution is optimized during chip-glass bondage.

2. 发明申请

US20100038692A1 Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors 有权
标题翻译：将I / O和核心MOS器件的形成与MOS电容器和电阻器集成
公开(公告)号：US20100038692A1
公开(公告)日：2010-02-18
申请号：US12191817
申请日：2008-08-14
申请人： Harry Chuang , Mong Song Liang , Wen-Chih Yang , Chien-Liang Chen , Chii-Horng Li
发明人： Harry Chuang , Mong Song Liang , Wen-Chih Yang , Chien-Liang Chen , Chii-Horng Li
IPC分类号： H01L27/11
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L28/20 , H01L28/40 , H01L29/94
摘要： An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.
摘要翻译：集成电路结构包括半导体衬底和第一和第二MOS器件。第一MOS器件包括半导体衬底上的第一栅极电介质，其中第一栅极电介质是平面的; 以及位于第一栅极电介质上的第一栅电极。第二MOS器件包括半导体衬底上的第二栅极电介质; 以及在所述第二栅极电介质上方的第二栅电极。第二栅电极的高度大于第一栅电极的高度。第二栅极电介质包括在第二栅电极下面的平面部分和在第二栅电极的侧壁上延伸的侧壁部分。

3. 发明授权

US08193586B2 Sealing structure for high-K metal gate 有权
标题翻译：高K金属门密封结构
公开(公告)号：US08193586B2
公开(公告)日：2012-06-05
申请号：US12389535
申请日：2009-02-20
申请人： Chien-Hao Chen , Hao-Ming Lien , Ssu-Yi Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang , Chien-Liang Chen
发明人： Chien-Hao Chen , Hao-Ming Lien , Ssu-Yi Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang , Chien-Liang Chen
IPC分类号： H01L21/02 , H01L21/8238
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译：本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域密封层的边缘。

4. 发明授权

US08003467B2 Method for making a semiconductor device having metal gate stacks 有权
标题翻译：制造具有金属栅叠层的半导体器件的方法
公开(公告)号：US08003467B2
公开(公告)日：2011-08-23
申请号：US12433356
申请日：2009-04-30
申请人： Jin-Aun Ng , Wen-Chih Yang , Chien-Liang Chen , Chung-Hau Fei , Maxi Chang , Bao-Ru Young , Harry Chuang
发明人： Jin-Aun Ng , Wen-Chih Yang , Chien-Liang Chen , Chung-Hau Fei , Maxi Chang , Bao-Ru Young , Harry Chuang
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.
摘要翻译：本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。

5. 发明申请

US20120225529A1 SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING 有权
标题翻译：高K金属门的密封结构及其制备方法
公开(公告)号：US20120225529A1
公开(公告)日：2012-09-06
申请号：US13465551
申请日：2012-05-07
申请人： Chieh-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
发明人： Chieh-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译：本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域密封层的边缘。

6. 发明申请

US20100109088A1 BALANCE STEP-HEIGHT SELECTIVE BI-CHANNEL STRUCTURE ON HKMG DEVICES 有权
标题翻译：平衡高级选择性双向通道结构在HKMG设备上
公开(公告)号：US20100109088A1
公开(公告)日：2010-05-06
申请号：US12433356
申请日：2009-04-30
申请人： Jin-Aun Ng , Wen-Chih Yang , Chien-Liang Chen , Chung-Hau Fei , Maxi Chang , Bao-Ru Young , Harry Chuang
发明人： Jin-Aun Ng , Wen-Chih Yang , Chien-Liang Chen , Chung-Hau Fei , Maxi Chang , Bao-Ru Young , Harry Chuang
IPC分类号： H01L27/092 , H01L21/20 , H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.
摘要翻译：本公开提供了一种方法，包括在硅衬底中形成STI特征，分别为PFET和NFET限定第一和第二有源区; 形成具有开口的硬掩模，以在所述第一有源区域内暴露所述硅衬底; 通过所述开口蚀刻所述硅衬底以在所述第一有源区内形成凹陷; 在凹部中生长SiGe层，使得第一有源区内的SiGe层的顶表面和第二有源区内的硅衬底的顶表面基本上是共面的; 形成金属栅材料层; 图案化金属栅极材料层以在第一有源区内的SiGe层上形成金属栅叠层; 以及在第一有源区内形成分布在SiGe层和硅衬底中的eSiGe S / D应力器。

7. 发明申请

US20090039433A1 SEMICONDUCTOR DEVICE WITH HIGH-K/DUAL METAL GATE 有权
标题翻译：具有高K /双金属栅的半导体器件
公开(公告)号：US20090039433A1
公开(公告)日：2009-02-12
申请号：US11836015
申请日：2007-08-08
申请人： Wen-Chih Yang , Chien-Liang Chen , Chii-Horng Lee , Harry Chuang
发明人： Wen-Chih Yang , Chien-Liang Chen , Chii-Horng Lee , Harry Chuang
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/82345
摘要： An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal layers have substantially different metallic compositions. The second semiconductor device includes a second gate electrode having a third metal layer forming a second trench and a fourth metal layer filling the second trench, wherein the third and fourth metal layers have substantially different metallic compositions, and wherein the first and third metal layers have substantially different metallic compositions.
摘要翻译：一种装置及其制造方法，包括第一半导体器件和第二半导体器件。第一半导体器件包括具有形成第一沟槽的第一金属层和填充第一沟槽的第二金属层的第一栅电极，其中第一和第二金属层具有基本不同的金属组成。第二半导体器件包括具有形成第二沟槽的第三金属层和填充第二沟槽的第四金属层的第二栅电极，其中第三和第四金属层具有基本上不同的金属组成，并且其中第一和第三金属层具有基本上不同的金属组成。

8. 发明申请

US20080308873A1 Semiconductor device with discontinuous CESL structure 有权
标题翻译：半导体器件具有不连续的CESL结构
公开(公告)号：US20080308873A1
公开(公告)日：2008-12-18
申请号：US11811693
申请日：2007-06-12
申请人： Chien-Liang Chen , Wen-Chih Yang , Chii-Horng Li , Harry Chuang
发明人： Chien-Liang Chen , Wen-Chih Yang , Chii-Horng Li , Harry Chuang
IPC分类号： H01L29/76 , H01L29/49
CPC分类号： H01L21/823807 , H01L29/66545 , H01L29/7843 , Y10S257/90
摘要： A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as a discontinuous layer. This may be done, for example, by depositing an appropriate CESL, then forming an ILD layer, and simultaneously reducing the ILD layer and the CESL to a desired level. The discontinuity preferably exposes the gate electrode, or the metal contact region formed on it, if present. The upper boundary of the CESL may be further reduced, however, to position it below the upper boundary of the gate electrode.
摘要翻译：使用CESL（接触蚀刻停止层）在例如CMOS晶体管沟道中诱发应变的半导体器件及其制造方法。在器件栅极结构上形成产生应力的CESL，n沟道器件中的拉伸和p沟道器件中的压缩，作为不连续层。这可以例如通过沉积适当的CESL，然后形成ILD层，同时将ILD层和CESL降低到期望的水平来完成。不连续性优选暴露栅电极或形成在其上的金属接触区域（如果存在）。然而，CESL的上边界可以进一步减小，以将其定位在栅电极的上边界以下。

9. 发明授权

US07915111B2 Semiconductor device with high-K/dual metal gate 有权
标题翻译：具有高K /双金属栅极的半导体器件
公开(公告)号：US07915111B2
公开(公告)日：2011-03-29
申请号：US11836015
申请日：2007-08-08
申请人： Wen-Chih Yang , Chien-Liang Chen , Chii-Horng Lee , Harry Chuang
发明人： Wen-Chih Yang , Chien-Liang Chen , Chii-Horng Lee , Harry Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/82345
摘要： An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal layers have substantially different metallic compositions. The second semiconductor device includes a second gate electrode having a third metal layer forming a second trench and a fourth metal layer filling the second trench, wherein the third and fourth metal layers have substantially different metallic compositions, and wherein the first and third metal layers have substantially different metallic compositions.
摘要翻译：一种装置及其制造方法，包括第一半导体器件和第二半导体器件。第一半导体器件包括具有形成第一沟槽的第一金属层和填充第一沟槽的第二金属层的第一栅电极，其中第一和第二金属层具有基本不同的金属组成。第二半导体器件包括具有形成第二沟槽的第三金属层和填充第二沟槽的第四金属层的第二栅电极，其中第三和第四金属层具有基本上不同的金属组成，并且其中第一和第三金属层具有基本上不同的金属组成。

10. 发明申请

US20100052072A1 DUAL GATE STRUCTURE ON A SAME CHIP FOR HIGH-K METAL GATE TECHNOLOGY 审中-公开
标题翻译：用于高K金属门技术的相同芯片的双门结构
公开(公告)号：US20100052072A1
公开(公告)日：2010-03-04
申请号：US12368044
申请日：2009-02-09
申请人： Chii-Horng Li , Po-Nien Chen , Chung-Hau Fei , Chien-Liang Chen , Wen-Chih Yang , Harry Chuang
发明人： Chii-Horng Li , Po-Nien Chen , Chung-Hau Fei , Chien-Liang Chen , Wen-Chih Yang , Harry Chuang
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0629
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. The method includes providing semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, removing the metal layer and capping layer in the second region, forming a polysilicon layer over the metal layer in the first region and over the high-k dielectric layer in the second region, and forming an active device with the metal layer in the first region and forming a passive device without the metal layer in the second region.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成金属层，金属层和覆盖层，在第一区域中的金属层上形成多晶硅层，并在第二区域中的高k电介质层上方形成多晶硅层，并在第一区域中形成具有金属层的有源器件，并形成在第二区域中没有金属层的无源器件。

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