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1. 发明授权

US07889541B2 2T SRAM cell structure 有权
标题翻译： 2T SRAM单元结构
公开(公告)号：US07889541B2
公开(公告)日：2011-02-15
申请号：US12422078
申请日：2009-04-10
申请人： Wei-Chiang Shih , Chen-Hao Po , Kwo-Jen Liu
发明人： Wei-Chiang Shih , Chen-Hao Po , Kwo-Jen Liu
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.
摘要翻译： SRAM单元结构包括第一N型交换机，第二N型交换机，第一存储节点和第二存储节点。第一N型开关具有连接到字线的控制端子和连接到位线的第一端子。第二N型开关具有连接到字线的控制端子和连接到反相位线的第一端子。第一存储节点具有连接到第一N型交换机的第二终端的第一终端。第二存储节点具有连接到第二N型交换机的第二终端的第一终端。

2. 发明授权

US08653878B2 Voltage switch circuit produced by logic circuit manufacturing process capable of withstanding high voltage stress 有权
标题翻译：电压开关电路由逻辑电路制造工艺生产，能承受高压应力
公开(公告)号：US08653878B2
公开(公告)日：2014-02-18
申请号：US13423411
申请日：2012-03-19
申请人： Chen-Hao Po , Chiun-Chi Shen
发明人： Chen-Hao Po , Chiun-Chi Shen
IPC分类号： H03L5/00
CPC分类号： H03K3/356104 , H03K3/356182 , H03K19/0175
摘要： A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.
摘要翻译：电压开关电路使用PMOS晶体管来承受高压应力。因此，NMOS晶体管不承受高电压应力。轻掺杂PMOS晶体管与逻辑电路制造工艺兼容。因此，可以通过逻辑电路制造工艺来产生电压开关电路。

3. 发明申请

US20130099850A1 VOLTAGE SWITCH CIRCUIT 有权
标题翻译：电压开关电路
公开(公告)号：US20130099850A1
公开(公告)日：2013-04-25
申请号：US13423411
申请日：2012-03-19
申请人： Chen-Hao Po , Chiun-Chi Shen
发明人： Chen-Hao Po , Chiun-Chi Shen
IPC分类号： H03K17/687
CPC分类号： H03K3/356104 , H03K3/356182 , H03K19/0175
摘要： A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.
摘要翻译：电压开关电路使用PMOS晶体管来承受高压应力。因此，NMOS晶体管不承受高电压应力。轻掺杂PMOS晶体管与逻辑电路制造工艺兼容。因此，可以通过逻辑电路制造工艺来产生电压开关电路。

4. 发明申请

US20060268642A1 Serial peripheral interface memory device with an accelerated parallel mode 有权
标题翻译：具有加速并行模式的串行外设接口存储器件
公开(公告)号：US20060268642A1
公开(公告)日：2006-11-30
申请号：US11137503
申请日：2005-05-26
申请人： Han-Sung Chen , Chia-Yen Yeh , Chen-Hao Po , Ching-Chung Lin
发明人： Han-Sung Chen , Chia-Yen Yeh , Chen-Hao Po , Ching-Chung Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/1075 , G11C5/066
摘要： A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.
摘要翻译：串行外围闪存器件使用多个虚拟输入/输出端子，以便能够对具有较慢串行时钟速度的器件选择并行模式。在并行模式下，通过多个虚拟输入/输出端子发送数据，以允许同时发送多个位，以较慢的串行时钟速度提高数据传输速率。

5. 发明授权

US06795350B2 Circuit and method for tuning a reference bit line loading to a sense amplifier by optionally cutting a capacitive reference bit line 有权
标题翻译：用于通过可选地切割电容性参考位线来将参考位线负载调谐到读出放大器的电路和方法
公开(公告)号：US06795350B2
公开(公告)日：2004-09-21
申请号：US10351528
申请日：2003-01-27
申请人： Han-Sung Chen , Kuo-Yu Liao , Chen-Hao Po , Chun-Hsiung Hung
发明人： Han-Sung Chen , Kuo-Yu Liao , Chen-Hao Po , Chun-Hsiung Hung
IPC分类号： G11C700
CPC分类号： G11C29/026 , G11C7/062 , G11C7/12 , G11C16/28 , G11C29/02 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2207/2254
摘要： A circuit and method for tuning a reference bit line loading to a sense amplifier that compares the voltage on a sense node with the voltage on a reference data line node to determine a sensing signal on the output of the sense amplifier. The sense node is selectively connected to a memory cell to generate the sensed voltage on the sense node to represent the data stored in the selected memory cell. There is included a reference cell unit and a reference bit line unit connected to the reference data line node. The reference cell unit contains at least one reference cell to provide a reference current to the reference bit line node, and the reference bit line unit contains at least one reference bit line optionally cut to determine the reference bit line loading.
摘要翻译：用于将参考位线加载到读出放大器的电路和方法，所述读出放大器将感测节点上的电压与参考数据线节点上的电压进行比较，以确定读出放大器的输出上的感测信号。感测节点被选择性地连接到存储器单元以在感测节点上产生感测的电压，以表示存储在所选择的存储器单元中的数据。包括连接到参考数据线节点的参考单元单元和参考位线单元。参考单元单元包含至少一个参考单元，以向参考位线节点提供参考电流，并且参考位线单元包含可选地切割的至少一个参考位线，以确定参考位线负载。

6. 发明申请

US20120268188A1 VOLATGE LEVEL SHIFTING APPARATUS 有权
公开(公告)号：US20120268188A1
公开(公告)日：2012-10-25
申请号：US13090283
申请日：2011-04-20
申请人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
发明人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
IPC分类号： H03L5/00
CPC分类号： H03K3/356182
摘要： A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.
摘要翻译：公开了一种电压电平转换装置。电压电平移位装置具有交叉耦合晶体管对，多个晶体管对，第一二极管串，第二二极管串和输入晶体管对。晶体管对中的一个耦合到交叉耦合晶体管对，并且晶体管对由多个参考电压控制。第一和第二二极管串耦合在两个晶体管对之间。第一和第二二极管串中的每一个具有至少一个二极管。输入晶体管对接收第一和第二输入电压，第一和第二输入电压是互补信号。交叉耦合晶体管对通过移位第一和第二输入电压的电压电平来产生并输出第一输出电压和第二输出电压。

7. 发明授权

US08373485B2 Voltage level shifting apparatus 有权
标题翻译：电压电平转换装置
公开(公告)号：US08373485B2
公开(公告)日：2013-02-12
申请号：US13090283
申请日：2011-04-20
申请人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
发明人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
IPC分类号： H03L5/00
CPC分类号： H03K3/356182
摘要： A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.
摘要翻译：公开了一种电压电平转换装置。电压电平移位装置具有交叉耦合晶体管对，多个晶体管对，第一二极管串，第二二极管串和输入晶体管对。晶体管对中的一个耦合到交叉耦合晶体管对，并且晶体管对由多个参考电压控制。第一和第二二极管串耦合在两个晶体管对之间。第一和第二二极管串中的每一个具有至少一个二极管。输入晶体管对接收第一和第二输入电压，第一和第二输入电压是互补信号。交叉耦合晶体管对通过移位第一和第二输入电压的电压电平来产生并输出第一输出电压和第二输出电压。

8. 发明申请

US20110194355A1 VERIFY WHILE WRITE SCHEME FOR NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：验证非易失性存储器单元的写入方案
公开(公告)号：US20110194355A1
公开(公告)日：2011-08-11
申请号：US12702258
申请日：2010-02-08
申请人： Chen-Hao Po
发明人： Chen-Hao Po
IPC分类号： G11C16/06
CPC分类号： G11C16/3468 , G11C16/10 , G11C16/24 , G11C16/3481
摘要： A verify while write (VWW) scheme for a non-volatile memory (NVM) cell is provided. The VWW scheme conducts simultaneous write and verify operation by sensing the memory cell current during the write pulse at exactly the same write bias condition in contrast to the “verify+retry-write” write algorithm in the prior art. The VWW scheme removes the iterative “verify and then retry-write” to save both control timing and power consumed in these iterations. Instead, the VWW scheme is composed of single write pulse only in the entire algorithm with exact write pulse width trimmed automatically for multiple memory cells undergoing parallel writing within one write command assertion. Faster write speed, more power efficient write operation and higher reliability of non-volatile semiconductor memory cell are thus achieved with the VWW scheme in this present disclosure.
摘要翻译：提供用于非易失性存储器（NVM）单元的写入验证（VWW）方案。与现有技术中的“验证+重试 - 写入”写入算法相反，VWW方案通过在写入脉冲期间以完全相同的写入偏置条件感测存储器单元电流来执行同时的写入和验证操作。 VWW方案消除迭代“验证然后重试”，以节省这些迭代中的控制时间和功耗。相反，VWW方案仅在整个算法中由单个写入脉冲组成，对于在一个写入命令断言中进行并行写入的多个存储单元，自动精确写入脉冲宽度。因此，本公开的VWW方案可以实现更快的写入速度，更高功率的写入操作和更高可靠性的非易失性半导体存储单元。

9. 发明授权

US07397717B2 Serial peripheral interface memory device with an accelerated parallel mode 有权
标题翻译：具有加速并行模式的串行外设接口存储器件
公开(公告)号：US07397717B2
公开(公告)日：2008-07-08
申请号：US11137503
申请日：2005-05-26
申请人： Han-Sung Chen , Chia-Yen Yeh , Chen-Hao Po , Ching-Chung Lin
发明人： Han-Sung Chen , Chia-Yen Yeh , Chen-Hao Po , Ching-Chung Lin
IPC分类号： G11C7/10
CPC分类号： G11C7/1075 , G11C5/066
摘要： A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.
摘要翻译：串行外围闪存器件使用多个虚拟输入/输出端子，以便能够对具有较慢串行时钟速度的器件选择并行模式。在并行模式下，通过多个虚拟输入/输出端子发送数据，以允许同时发送多个位，以较慢的串行时钟速度提高数据传输速率。

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