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1. 发明申请

US20130193511A1 VERTICAL TRANSISTOR STRUCTURE 审中-公开
标题翻译：垂直晶体管结构
公开(公告)号：US20130193511A1
公开(公告)日：2013-08-01
申请号：US13358823
申请日：2012-01-26
申请人： Hsuan-Yu FANG , Wei-Chih Liu , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang , Kazuaki Takesako , Tomohiro Kadoya , Wen Kuei Hsu , Hirotake Fujita , Yukihiro Nagai , Chih-Wei Hsiung , Yoshinori Tanaka
发明人： Hsuan-Yu FANG , Wei-Chih Liu , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang , Kazuaki Takesako , Tomohiro Kadoya , Wen Kuei Hsu , Hirotake Fujita , Yukihiro Nagai , Chih-Wei Hsiung , Yoshinori Tanaka
IPC分类号： H01L27/088
CPC分类号： H01L29/7827 , H01L29/4236 , H01L29/66666
摘要： A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.
摘要翻译：垂直晶体管结构包括基板，形成在基板上并彼此间隔开的多个柱，每个形成在两个相邻柱之间的多个沟槽，形成在第一侧壁的表面上的保护层和沟槽的第二侧壁，分别形成在第一侧壁和第二侧壁的保护层上的第一栅极和第二栅极以及覆盖沟槽底壁的分离层。本发明在蚀刻时使用用作蚀刻停止层的分离层到第一栅极和第二栅极。此外，分离层的厚度用于控制底壁和第一和第二栅极之间的距离，并且通过离子注入限定在柱中形成的漏极和源极的宽度。

2. 发明授权

US08956961B2 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08956961B2
公开(公告)日：2015-02-17
申请号：US13415959
申请日：2012-03-09
申请人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
发明人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
IPC分类号： H01L21/02
CPC分类号： H01L21/2257 , H01L21/2236 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
摘要翻译：半导体器件包括：具有基底和从基底延伸的半导体柱阵列的衬底，衬底形成有多个沟槽，每个沟槽延伸到衬底中并且具有两个相对的沟槽侧壁; 第一绝缘衬垫层，其形成在每个沟槽的每个沟槽侧壁上，并且通过间隙留下每个沟槽侧壁的位形成表面，该间隙未被第一绝缘衬垫层覆盖; 以及多个掩埋位线，每个埋入位线从每个沟槽的相应一个沟槽侧壁的位形成表面延伸到基座中。

3. 发明申请

US20130234230A1 Semiconductor Device and Method for Making the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130234230A1
公开(公告)日：2013-09-12
申请号：US13415959
申请日：2012-03-09
申请人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
发明人： Kazuaki Takesako , Wen-Kuei Hsu , Yoshinori Tanaka , Yukihiro Nagai , Chih-Wei Hsiung , Hirotake Fujita , Tomohiro Kadoya , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Chung-Yung Ai , Yu-Shan Hsu , Wei-Che Chang , Chun-Hua Huang
IPC分类号： H01L27/105 , H01L21/225
CPC分类号： H01L21/2257 , H01L21/2236 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
摘要翻译：半导体器件包括：具有基底和从基底延伸的半导体柱阵列的衬底，衬底形成有多个沟槽，每个沟槽延伸到衬底中并且具有两个相对的沟槽侧壁; 第一绝缘衬垫层，其形成在每个沟槽的每个沟槽侧壁上，并且通过间隙留下每个沟槽侧壁的位形成表面，该间隙未被第一绝缘衬垫层覆盖; 以及多个掩埋位线，每个埋入位线从每个沟槽的相应一个沟槽侧壁的位形成表面延伸到基座中。

4. 发明申请

US20130157454A1 SELF-ALIGNED WET ETCHING PROCESS 有权
标题翻译：自对准湿蚀刻过程
公开(公告)号：US20130157454A1
公开(公告)日：2013-06-20
申请号：US13327157
申请日：2011-12-15
申请人： Wei-Che CHANG , Chun-Hua Huang , Chung-Yung Ai , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Yu-Shan Hsu , Kazuaki Takesako , Hirotake Fujita , Tomohiro Kadoya , Wen Kuei Hsu , Chih-Wei Hsiung , Yukihiro Nagai , Yoshinori Tanaka
发明人： Wei-Che CHANG , Chun-Hua Huang , Chung-Yung Ai , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Yu-Shan Hsu , Kazuaki Takesako , Hirotake Fujita , Tomohiro Kadoya , Wen Kuei Hsu , Chih-Wei Hsiung , Yukihiro Nagai , Yoshinori Tanaka
IPC分类号： H01L21/28
CPC分类号： H01L29/66666 , H01L27/10876
摘要： A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
摘要翻译：自对准湿蚀刻工艺包括以下步骤：在其表面上蚀刻具有蚀刻保护层的衬底，以形成彼此间隔开的多个沟槽; 并且在每个沟槽中依次形成绝缘层，蚀刻停止层和初级绝缘体，其中所述初级绝缘体填充在由所述蚀刻停止层包围的容纳空间的内部。在湿蚀刻工艺期间，蚀刻停止层保护初级绝缘体不被蚀刻，从而实现各向异性湿蚀刻。此外，本发明扩大了与外部电路电连接的接触面积，并且免除了形成在接触区域上的电接触器由于过度蚀刻初级绝缘体而引起的短路。

5. 发明授权

US08461056B1 Self-aligned wet etching process 有权
标题翻译：自对准湿法蚀刻工艺
公开(公告)号：US08461056B1
公开(公告)日：2013-06-11
申请号：US13327157
申请日：2011-12-15
申请人： Wei-Che Chang , Chun-Hua Huang , Chung-Yung Ai , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Yu-Shan Hsu , Kazuaki Takesako , Hirotake Fujita , Tomohiro Kadoya , Wen Kuei Hsu , Chih-Wei Hsiung , Yukihiro Nagai , Yoshinori Tanaka
发明人： Wei-Che Chang , Chun-Hua Huang , Chung-Yung Ai , Wei-Chih Liu , Hsuan-Yu Fang , Yu-Ling Huang , Meng-Hsien Chen , Chun-Chiao Tseng , Yu-Shan Hsu , Kazuaki Takesako , Hirotake Fujita , Tomohiro Kadoya , Wen Kuei Hsu , Chih-Wei Hsiung , Yukihiro Nagai , Yoshinori Tanaka
IPC分类号： H01L21/302
CPC分类号： H01L29/66666 , H01L27/10876
摘要： A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
摘要翻译：自对准湿蚀刻工艺包括以下步骤：在其表面上蚀刻具有蚀刻保护层的衬底，以形成彼此间隔开的多个沟槽; 并且在每个沟槽中依次形成绝缘层，蚀刻停止层和初级绝缘体，其中所述初级绝缘体填充在由所述蚀刻停止层包围的容纳空间的内部。在湿蚀刻工艺期间，蚀刻停止层保护初级绝缘体不被蚀刻，从而实现各向异性湿蚀刻。此外，本发明扩大了与外部电路电连接的接触面积，并且免除了形成在接触区域上的电接触器由于过度蚀刻初级绝缘体而引起的短路。

6. 发明申请

US20110169062A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110169062A1
公开(公告)日：2011-07-14
申请号：US12982342
申请日：2010-12-30
申请人： Tomohiro Kadoya
发明人： Tomohiro Kadoya
IPC分类号： H01L27/108 , H01L27/088
CPC分类号： H01L27/088 , H01L21/76895 , H01L21/823475 , H01L27/0207 , H01L27/10852 , H01L27/10855 , H01L27/10888 , H01L27/10894 , H01L28/91
摘要： A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion.
摘要翻译：半导体器件包括以下元件。元件隔离部分分离半导体衬底中的第一和第二扩散区域。第一绝缘膜形成在元件隔离部分和第一和第二扩散区域上。第一和第二接触塞分别形成在第一和第二扩散区上。第一和第二接触插塞穿透第一绝缘膜。在元件隔离部分上方的第一绝缘膜上形成第一导电层。在第一导电层上形成第二绝缘膜。第三接触插塞穿透第二绝缘膜，第三接触插塞连接第一接触插塞。在与第三接触插塞接触的第二绝缘膜上形成第二导电层。第一和第二导电层部分地与元件隔离部分重叠。

7. 发明授权

US08399916B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08399916B2
公开(公告)日：2013-03-19
申请号：US13412535
申请日：2012-03-05
申请人： Tomohiro Kadoya
发明人： Tomohiro Kadoya
IPC分类号： H01L27/092
CPC分类号： H01L27/10814 , H01L27/10852 , H01L28/90
摘要： A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.
摘要翻译：具有尺寸由设计规则F的数值定义的6F2存储单元的半导体器件，其中包括在存储单元中的电容器的下电极由支撑膜支撑; 支撑膜形成为将在第一方向上线性延伸的第一支撑图案（14x）和沿与第一方向相反的第二方向线性延伸的第二支撑图案（14y）组合的图案; 支撑膜布置成使得第一和第二支撑图案的间隔都等于或大于1.5F; 并且所述第一和第二支撑图案之一的间隔大于所述第一和第二支撑图案中的另一个的间隔。

8. 发明授权

US09209192B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09209192B2
公开(公告)日：2015-12-08
申请号：US12982342
申请日：2010-12-30
申请人： Tomohiro Kadoya
发明人： Tomohiro Kadoya
IPC分类号： H01L27/108 , H01L21/768 , H01L49/02 , H01L21/8234 , H01L27/02
CPC分类号： H01L27/088 , H01L21/76895 , H01L21/823475 , H01L27/0207 , H01L27/10852 , H01L27/10855 , H01L27/10888 , H01L27/10894 , H01L28/91
摘要： A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion.
摘要翻译：半导体器件包括以下元件。元件隔离部分分离半导体衬底中的第一和第二扩散区域。第一绝缘膜形成在元件隔离部分和第一和第二扩散区域上。第一和第二接触塞分别形成在第一和第二扩散区上。第一和第二接触插塞穿透第一绝缘膜。在元件隔离部分上方的第一绝缘膜上形成第一导电层。在第一导电层上形成第二绝缘膜。第三接触插塞穿透第二绝缘膜，第三接触插塞连接第一接触插塞。在与第三接触插塞接触的第二绝缘膜上形成第二导电层。第一和第二导电层部分地与元件隔离部分重叠。

9. 发明授权

US08134398B2 Device having gate with two buried portions with different widths 有权
标题翻译：具有具有两个具有不同宽度的埋藏部分的门的装置
公开(公告)号：US08134398B2
公开(公告)日：2012-03-13
申请号：US12946030
申请日：2010-11-15
申请人： Tomohiro Kadoya
发明人： Tomohiro Kadoya
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10894 , H01L29/4236 , H01L29/4238 , H01L29/7834
摘要： A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction.
摘要翻译：虚设晶体管和场效应晶体管沿第二方向排列。虚拟晶体管至少位于第二方向的一端。

10. 发明授权

US08129769B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08129769B2
公开(公告)日：2012-03-06
申请号：US12638465
申请日：2009-12-15
申请人： Tomohiro Kadoya
发明人： Tomohiro Kadoya
IPC分类号： H01L27/092
CPC分类号： H01L27/10814 , H01L27/10852 , H01L28/90
摘要： A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.
摘要翻译：具有尺寸由设计规则F的数值定义的6F2存储单元的半导体器件，其中包括在存储单元中的电容器的下电极由支撑膜支撑; 支撑膜形成为将在第一方向上线性延伸的第一支撑图案（14x）和沿与第一方向相反的第二方向线性延伸的第二支撑图案（14y）组合的图案; 支撑膜布置成使得第一和第二支撑图案的间隔都等于或大于1.5F; 并且所述第一和第二支撑图案之一的间隔大于所述第一和第二支撑图案中的另一个的间隔。

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