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1. 发明申请

US20140210014A1 METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION 有权
标题翻译：在标准电池配置中用金属化电阻形成集成电路的方法和装置
公开(公告)号：US20140210014A1
公开(公告)日：2014-07-31
申请号：US13779783
申请日：2013-02-28
申请人： Wei Yu MA , Bo-Ting CHEN , Ting Yu CHEN , Kuo-Ji CHEN , Li-Chun TIEN
发明人： Wei Yu MA , Bo-Ting CHEN , Ting Yu CHEN , Kuo-Ji CHEN , Li-Chun TIEN
IPC分类号： H01L27/02
CPC分类号： H01L27/0288 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/0248 , H01L27/0629 , H01L27/11807 , H01L28/20 , H01L28/24
摘要： An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.
摘要翻译：集成电路包括半导体器件层，其包括在栅电极线之间具有固定栅电极间距的标准单元配置和在标准单元配置的固定栅电极间距之间由金属形成的电阻。在一个实施例中，集成电路可以是具有由金属形成的电阻器的交叉域标准单元的充电器件模型（CDM）静电放电（ESD）保护电路。制造集成电路的方法包括：形成由栅电极间距分开的多个栅极电极线，以形成芯标准电池器件，在栅电极间距内施加至少第一金属层以形成电阻器的一部分，以及施加至少第二金属层以耦合到第一金属层以形成电阻器的另一部分。

2. 发明申请

US20130119449A1 SEMICONDUCTOR DEVICE WITH SEAL RING WITH EMBEDDED DECOUPLING CAPACITOR 有权
标题翻译：带封装解密电容器的密封圈的半导体器件
公开(公告)号：US20130119449A1
公开(公告)日：2013-05-16
申请号：US13296410
申请日：2011-11-15
申请人： Kuo-Ji CHEN , Wei Yu MA , Ta-Pen GUO , Hsien-Wei CHEN , Hao-Yi TSAI
发明人： Kuo-Ji CHEN , Wei Yu MA , Ta-Pen GUO , Hsien-Wei CHEN , Hao-Yi TSAI
IPC分类号： H01L29/94 , H01L29/93
CPC分类号： H01L29/93 , H01L23/5223 , H01L23/5286 , H01L23/585 , H01L27/0629 , H01L27/0805 , H01L28/60 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.
摘要翻译：用于半导体器件的密封环设置有嵌入式去耦电容器。密封环外围围绕密封环区域中的集成电路芯片。至少一个嵌入式去耦电容器可以包括MOS电容器，变容二极管，MOM电容器和具有多个电容器板耦合在一起的叉指电容器。相对的电容器板耦合到不同的电位，并且可以有利地耦合到Vdd和Vss。

3. 发明申请

US20130093052A1 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A RESISTOR AND METHOD OF FORMING THE SAME 有权
标题翻译：具有电阻器的半导体集成电路及其形成方法
公开(公告)号：US20130093052A1
公开(公告)日：2013-04-18
申请号：US13272389
申请日：2011-10-13
申请人： Wei Yu MA , Kuo-Ji CHEN , Fang-Tsun CHU , Ta-Pen GUO
发明人： Wei Yu MA , Kuo-Ji CHEN , Fang-Tsun CHU , Ta-Pen GUO
IPC分类号： H01L27/06 , H01L21/768
CPC分类号： H01L27/0266 , H01L21/76895 , H01L23/5228 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.
摘要翻译：本申请公开了一种半导体集成电路，包括其上形成有电气器件的衬底，形成在衬底上的局部互连层，以及形成在局部互连层上的全局互连层。局部互连层具有第一组导电结构，其布置成在各个电气设备之间，电气设备及其相邻的电气设备之一中，或垂直设备和全局互连层之间电连接。第一组导电结构中的至少一个被配置为具有大于50欧姆的电阻值。全局互连层具有布置成经由第一组导电结构电连接电器件的第二组导电结构。

4. 发明申请

US20130235497A1 ELECTRO-STATIC DISCHARGE CLAMP (ESD) FOR NxVDD POWER RAIL 有权
标题翻译：用于NxVDD电力轨的电动放电钳（ESD）
公开(公告)号：US20130235497A1
公开(公告)日：2013-09-12
申请号：US13415621
申请日：2012-03-08
申请人： Wei Yu MA
发明人： Wei Yu MA
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： A circuit with an electro-static discharge clamp coupled to a first power source and second power source. The electro-static discharge clamp includes an NMOS stack and an electro-static discharge detector. The NMOS stack has a first NMOS transistor with gate node ng1 and a second NMOS transistor with gate node ng2. The electro-static discharge detector is configured to control the NMOS stack, and may include three switches. A first switch is configured to switch the gate node ng1 to the second power source. A second switch is configured to switch the gate node ng1 to the gate node ng2. A third switch is configured to switch the gate node ng1 to the ground.
摘要翻译：具有耦合到第一电源和第二电源的静电放电钳的电路。静电放电钳包括NMOS堆叠和静电放电检测器。 NMOS堆叠具有具有栅极节点ng1的第一NMOS晶体管和具有栅极节点ng2的第二NMOS晶体管。静电放电检测器被配置为控制NMOS堆叠，并且可以包括三个开关。第一开关被配置为将门节点ng1切换到第二电源。第二开关被配置为将门节点ng1切换到门节点ng2。第三开关被配置为将门节点ng1切换到地。

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