专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060168552A1 Substrate mapping 审中-公开
标题翻译：基板映射
公开(公告)号：US20060168552A1
公开(公告)日：2006-07-27
申请号：US11386474
申请日：2006-03-22
申请人： Warren Farnworth , Derek Gochnour
发明人： Warren Farnworth , Derek Gochnour
IPC分类号： G06F17/50
CPC分类号： H01L23/544 , H01L24/83 , H01L2223/54413 , H01L2223/5442 , H01L2223/54473 , H01L2223/54486 , H01L2224/83192 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , Y10T29/49004 , Y10T29/49146 , Y10T29/53043 , Y10T29/53178 , Y10T29/53187 , H01L2924/00
摘要： A method for fabricating semiconductor die packages and semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
摘要翻译：一种制造半导体管芯封装和半导体管芯封装的方法，包括安装衬底和附着于其上的裸片。安装基板包括多个管芯附接位置和具有衬底识别信息的指示符。芯片附着位点被评估并分类为良好或有缺陷的裸片附着位点，其中所评估的信息作为映射信息保存在电子文件中。根据信息将模具附接到管芯附着位置，其中已知的好的裸片附接到良好的裸片附着位置，并且已知的有缺陷的裸片附着到有缺陷的芯片附着位置。然后将组件封装在传递模制操作中。

2. 发明申请

US20050101158A1 Methods for forming protective layers on semiconductor device substrates 失效
标题翻译：在半导体器件基板上形成保护层的方法
公开(公告)号：US20050101158A1
公开(公告)日：2005-05-12
申请号：US11012569
申请日：2004-12-15
申请人： Warren Farnworth , Warren Farnworth
发明人： Warren Farnworth , Warren Farnworth
IPC分类号： H01L23/31 , H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L21/44 , B33Y10/00 , B33Y30/00 , B33Y40/00 , B33Y80/00 , H01L23/3157 , H01L23/3192 , H01L2924/00013 , H01L2924/0002 , H01L2224/29099 , H01L2924/00
摘要： Methods for forming protective layers on semiconductor devices, including semiconductor devices that are carried by fabrication substrates, that are parts of assemblies, and that include individual dies, includes at least partially consolidating previously unconsolidated material selectively, in accordance with a program. The method may include use of a machine vision system or other object recognition apparatus to provide precise die-specific alignment. A protective structure may be formed to include at least one layer or segment of dielectric material having a controlled thickness or depth and a precise boundary. The layer or segment may include precisely sized, shaped, and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. Dielectric material may also be employed as a structure to mechanically reinforce a die-to-substrate (e.g., die-to-lead frame) attachment.
摘要翻译：在半导体器件上形成保护层的方法，包括由制造衬底承载的半导体器件，其是组件的部件，并且包括单独的裸片，包括根据程序选择性地至少部分地固结先前未合并的材料。该方法可以包括使用机器视觉系统或其他物体识别装置来提供精确的模具特异性对准。可以形成保护结构以包括具有受控厚度或深度和精确边界的至少一个介电材料层或段。层或段可以包括精确尺寸的，成形的和定位的孔，通过该孔可以访问管芯表面上的导电端子，例如接合焊盘。电介质材料也可以用作结构以机械加强芯片到基板（例如，管芯到引线框架）的连接。

3. 发明授权

US07785915B2 Wafer level method of locating focal plane of imager devices 有权
标题翻译：定位成像设备焦平面的晶片级方法
公开(公告)号：US07785915B2
公开(公告)日：2010-08-31
申请号：US11554243
申请日：2006-10-30
申请人： Warren Farnworth
发明人： Warren Farnworth
IPC分类号： H01L21/00 , H01L21/30
CPC分类号： H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14685 , H01L27/14689 , H01L2224/48091 , H01L2924/15174 , H04N5/2257 , H01L2924/00014
摘要： A method is disclosed which includes providing an imager substrate comprised of at least one imager device, providing a transparent substrate, forming a plurality of standoff structures on one of the imager substrate and the transparent substrate, the standoff structures having a width, forming an adhesive material having an initial thickness on a surface on at least one of the standoff structures, the adhesive material having an initial width that is less than the width of the standoff structures, and urging one of the imager substrate and the transparent substrate toward the other until such time as the imager substrate and the transparent substrate are in proper focal position relative to one another, the urging causing the initial thickness of the adhesive material to be reduced to a final thickness that is less than the initial thickness.
摘要翻译：公开了一种方法，其包括提供由至少一个成像器装置构成的成像器衬底，提供透明衬底，在成像器衬底和透明衬底之一上形成多个间隔结构，间隔结构具有宽度，形成粘合剂在至少一个支座结构上的表面上具有初始厚度的材料，所述粘合材料具有小于所述支座结构的宽度的初始宽度，并且将所述成像器基板和所述透明基板中的一个朝向另一个，直到像成像器基板和透明基板相对于彼此处于适当的焦点位置的时间，使粘合剂材料的初始厚度减小到小于初始厚度的最终厚度的推动。

4. 发明申请

US20090032964A1 System and method for providing semiconductor device features using a protective layer 审中-公开
标题翻译：使用保护层提供半导体器件特征的系统和方法
公开(公告)号：US20090032964A1
公开(公告)日：2009-02-05
申请号：US11888122
申请日：2007-07-31
申请人： Warren Farnworth , Kyle Kirby
发明人： Warren Farnworth , Kyle Kirby
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/525 , H01L24/10 , H01L24/12 , H01L24/13 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01033 , H01L2924/14 , H01L2924/19042 , H01L2924/3025 , H01L2224/05552 , H01L2924/00
摘要： Present embodiments relate to systems and methods for providing semiconductor device features using a protective layer during coating operations. One embodiment includes a method comprising providing a substrate with a hole formed partially therethrough, the hole comprising an opening in a first side of the substrate. Additionally, the method comprises disposing a protective layer over the first side of the substrate, removing a portion of the protective layer over at least a portion of the opening to provide access to the hole, and filling at least a portion of the hole with a fill material.
摘要翻译：本实施例涉及在涂覆操作期间使用保护层提供半导体器件特征的系统和方法。一个实施例包括一种方法，其包括提供基底部分穿过其中形成的孔，所述孔包括在所述基底的第一侧中的开口。另外，该方法包括在衬底的第一侧上设置保护层，在开口的至少一部分上移除保护层的一部分以提供对孔的接近，以及用孔填充孔的至少一部分填充材料。

5. 发明申请

US20080029851A1 METHODS OF FORMING CONDUCTIVE VIAS AND METHODS OF FORMING MULTICHIP MODULES INCLUDING SUCH CONDUCTIVE VIAS 有权
标题翻译：形成导电VIAS的方法和形成包括这种导电VIAS的多模块模块的方法
公开(公告)号：US20080029851A1
公开(公告)日：2008-02-07
申请号：US11868899
申请日：2007-10-08
申请人： Kyle Kirby , Warren Farnworth
发明人： Kyle Kirby , Warren Farnworth
IPC分类号： H01L29/40
CPC分类号： B82Y10/00 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2221/1094 , H01L2224/05001 , H01L2224/05009 , H01L2224/05548 , H01L2224/0557 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2224/05599 , H01L2224/05099
摘要： A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric material, a plurality of smaller through-holes may be formed in the dielectric material, and conductive material may be deposited in the smaller holes. Another method includes forming laterally separated protruding structures in a cavity of a substrate, depositing conductive material over the structures and dielectric material between the structures, and thinning the substrate. Alternatively, conductive nanotubes may be formed in the cavity, and dielectric material may be deposited that surrounds the nanotubes. A method of forming a multichip module includes forming at least one via extending through a plurality of stacked dice that includes a plurality of conductive elements.
摘要翻译：形成多导体通孔的方法包括在衬底的至少一个通孔中形成至少一个种子层，选择性地图案化种子层以形成多个横向分离的区域，并在该区域上沉积金属。或者，通孔可以基本上填充有介电材料，可以在电介质材料中形成多个较小的通孔，并且导电材料可以沉积在较小的孔中。另一种方法包括在衬底的空腔中形成横向分离的突出结构，在结构之间沉积导电材料并在该结构之间沉积电介质材料，并使衬底变薄。或者，可以在空腔中形成导电纳米管，并且可以沉积围绕纳米管的电介质材料。一种形成多芯片模块的方法包括形成至少一个通过包括多个导电元件的多个堆叠的骰子延伸的通孔。

6. 发明申请

US20080011815A1 METHODS FOR PLACING SUBSTRATES IN CONTACT WITH MOLTEN SOLDER 审中-公开
标题翻译：用于安装与MOLTEN SOLDER接触的基板的方法
公开(公告)号：US20080011815A1
公开(公告)日：2008-01-17
申请号：US11777137
申请日：2007-07-12
申请人： Kyle Kirby , Salman Akram , Daniel Cram , Roy Lange , Warren Farnworth
发明人： Kyle Kirby , Salman Akram , Daniel Cram , Roy Lange , Warren Farnworth
IPC分类号： B23K31/02
CPC分类号： B23K1/085 , B23K1/0016 , B23K3/0653 , B23K2101/40
摘要： Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder bath, a nozzle for producing a solder wave, and a jig for orienting a substrate in a substantially vertical orientation and placing the substrate in contact with a cascading solder wave. In another wave soldering apparatus, a jig orients a semiconductor wafer in a substantially horizontal orientation in contact with the solder wave. Another soldering apparatus includes a tank comprising molten solder and a fixture configured to orient one or more semiconductor wafers in a substantially vertical orientation. Methods of placing semiconductor wafers or other substrates in contact with solder using the devices of the present invention are also disclosed.
摘要翻译：描述了将半导体晶片或其它基板与焊料接触的方法和装置。波峰焊装置包括焊料槽，用于产生焊波的喷嘴和用于使基板垂直定向的夹具，并使基板与级联焊波接触。在另一种波峰焊装置中，夹具使得与焊波接触的大致水平取向的半导体晶片。另一个焊接装置包括一个包含熔融焊料和一个被配置为使一个或多个半导体晶片呈基本垂直取向取向的夹具的罐。还公开了使用本发明的装置将半导体晶片或其它基板与焊料接触的方法。

7. 发明申请

US20070285115A1 UNIVERSAL WAFER CARRIER FOR WAFER LEVEL DIE BURN-IN 失效
标题翻译：通用水平滚轮加速器
公开(公告)号：US20070285115A1
公开(公告)日：2007-12-13
申请号：US11841566
申请日：2007-08-20
申请人： Alan Wood , Tim Corbett , Warren Farnworth
发明人： Alan Wood , Tim Corbett , Warren Farnworth
IPC分类号： G01R31/02 , G01R1/06
CPC分类号： G01R31/2863
摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
摘要翻译：用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。刚性基板在其上具有与晶片电接触的导体。在老化和电气测试完成之前，测试夹具不需要打开。在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

8. 发明申请

US20070170350A1 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
公开(公告)号：US20070170350A1
公开(公告)日：2007-07-26
申请号：US11727545
申请日：2007-03-27
申请人： Warren Farnworth , Sidney Rigg , William Hiatt , Alan Wood , Peter Benson , James Wark , David Hembree , Kyle Kirby , Charles Watkins , Salman Akram
发明人： Warren Farnworth , Sidney Rigg , William Hiatt , Alan Wood , Peter Benson , James Wark , David Hembree , Kyle Kirby , Charles Watkins , Salman Akram
IPC分类号： H01L27/00
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

9. 发明申请

US20070134359A1 Apparatus for use in stereolithographic processing of components and assemblies 审中-公开
标题翻译：用于组件和组件的立体光刻处理的设备
公开(公告)号：US20070134359A1
公开(公告)日：2007-06-14
申请号：US11702473
申请日：2007-02-05
申请人： Warren Farnworth
发明人： Warren Farnworth
IPC分类号： B29C35/08
CPC分类号： G03F7/70416 , B29C64/106 , B29C64/135 , B33Y30/00 , B33Y40/00 , B33Y50/02 , G03F7/0037
摘要： An apparatus for providing gross location, planarization, and mechanical restraint to one or more electronic components such as semiconductor dice to be subjected to stereolithographic processing. A double platen assembly including a first platen and a second platen mutually removably connected and configured and arranged to substantially secure an electronic component assembly in position therebetween. At least one of the platens is configured such that a portion of electronic components of a carrier substrate secured by the double platen assembly is viewable for exposure to an energy beam such as a laser beam used to cure a liquid into an associated dielectric stereolithographic packaging structure. Another embodiment includes the use of an adhesive-coated film for holding, locating and securing a plurality of individual electronic components for processing. A method of forming solder balls is also disclosed.
摘要翻译：一种用于向诸如要进行立体光刻处理的半导体晶片的一个或多个电子部件提供总位置，平面化和机械约束的装置。双压板组件包括第一压板和第二压板，所述第一压板和第二压板相互可拆卸地连接并构造和布置成基本上将电子部件组件固定在其间的适当位置。至少一个压板被构造成使得由双压板组件固定的载体基板的电子部件的一部分可见以暴露于能量束，例如用于将液体固化成相关的介电立体光刻封装结构的激光束。另一个实施例包括使用粘合剂涂覆膜来保持，定位和固定多个单独的电子部件进行加工。还公开了形成焊球的方法。

10. 发明申请

US20070075725A1 Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer 失效
标题翻译：用于从半导体晶片上的其它IC隔离短路集成电路（IC）的装置和方法
公开(公告)号：US20070075725A1
公开(公告)日：2007-04-05
申请号：US11607367
申请日：2006-12-01
申请人： Warren Farnworth , William Waller , Leland Nevill , Raymond Beffa , Eugene Cloud
发明人： Warren Farnworth , William Waller , Leland Nevill , Raymond Beffa , Eugene Cloud
IPC分类号： G01R31/26
CPC分类号： G01R31/025 , G01R31/2884
摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.
摘要翻译：用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路电路。控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式