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1. 发明申请

US20050186744A1 MOSFET with decoupled halo before extension 失效
标题翻译：扩展前分离光环的MOSFET
公开(公告)号：US20050186744A1
公开(公告)日：2005-08-25
申请号：US10785895
申请日：2004-02-24
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier, , Carl Radens , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier, , Carl Radens , William Tonti
IPC分类号： H01L21/28 , H01L21/336 , H01L21/425 , H01L21/8234 , H01L29/423
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/6659
摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.
摘要翻译：反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响旨在改变装置的串联电阻。逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

2. 发明申请

US20070170521A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 有权
公开(公告)号：US20070170521A1
公开(公告)日：2007-07-26
申请号：US11306827
申请日：2006-01-12
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

3. 发明申请

US20070127172A1 ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING 失效
标题翻译：使用光电传感器的需求电路功能执行
公开(公告)号：US20070127172A1
公开(公告)日：2007-06-07
申请号：US11275058
申请日：2005-12-06
申请人： Wagdi Abadeer , James Adkisson , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Michael Hauser , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , James Adkisson , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Michael Hauser , Jed Rankin , William Tonti
IPC分类号： H02H9/00
CPC分类号： H01L23/5256 , H01L23/525 , H01L27/14609 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.
摘要翻译：公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。一旦封装的芯片放置在系统中，也可以将ESD保护装置从输入焊盘断开。不需要额外的引脚。

4. 发明申请

US20070284669A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 审中-公开
公开(公告)号：US20070284669A1
公开(公告)日：2007-12-13
申请号：US11838934
申请日：2007-08-15
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthier , Jed Rankin , William Tonti
IPC分类号： H01L29/76
CPC分类号： B07C5/344 , G01R31/2831
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

5. 发明申请

US20070292996A1 METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 有权
标题翻译：加工薄膜和薄膜的方法和结构以及可变的熔化到熔融间隙
公开(公告)号：US20070292996A1
公开(公告)日：2007-12-20
申请号：US11846544
申请日：2007-08-29
申请人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthler , Jed Rankin , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , Kiran Chatty , Robert Gauthler , Jed Rankin , William Tonti
IPC分类号： H01L21/84
CPC分类号： B07C5/344 , G01R31/2831
摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.
摘要翻译：公开了一种集成电路，其具有在相同基板上具有不同宽度和可变间隔的多个半导体散热片。形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET，或者替代地，各种单鳍和/或多鳍FET。

6. 发明申请

US20060091951A1 INTEGRATED CIRCUIT AMPLIFIER DEVICE AND METHOD USING FET TUNNELING GATE CURRENT 失效
标题翻译：集成电路放大器装置及使用FET隧道栅极电流的方法
公开(公告)号：US20060091951A1
公开(公告)日：2006-05-04
申请号：US10904238
申请日：2004-10-29
申请人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
发明人： Wagdi Abadeer , Anthony Bonaccio , Kiran Chatty , John Fifield
IPC分类号： H03F3/45 , H03F3/16
CPC分类号： H03F3/16 , H03F3/45179 , H03F3/505 , H03F2203/45468
摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.
摘要翻译：在示例性实施例中，集成电路放大器包括被配置为源极跟随器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极跟随器以便设置放大器的输出电导。

7. 发明申请

US20060157799A1 LOW TRIGGER VOLTAGE, LOW LEAKAGE ESD NFET 失效
标题翻译：低触发电压，低漏电ESD NFET
公开(公告)号：US20060157799A1
公开(公告)日：2006-07-20
申请号：US10905682
申请日：2005-01-17
申请人： Kiran Chatty , Robert Gauthier , Terence Hook , Christopher Putnam , Mujahid Muhammad
发明人： Kiran Chatty , Robert Gauthier , Terence Hook , Christopher Putnam , Mujahid Muhammad
IPC分类号： H01L29/76
CPC分类号： H01L29/78 , H01L27/027
摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.
摘要翻译：具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于衬底的沟道区域。此外，衬底的降低的触发电压区域位于漏极区域的下方。降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。因此，降低的触发电压区域没有注入的N型和P型掺杂。

8. 发明申请

US20060072267A1 HIGH VOLTAGE ESD POWER CLAMP 失效
标题翻译：高电压ESD功率钳位
公开(公告)号：US20060072267A1
公开(公告)日：2006-04-06
申请号：US10711748
申请日：2004-10-01
申请人： Kiran Chatty , Robert Gauthier , Mahmoud Mousa , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mahmoud Mousa , Mujahid Muhammad , Christopher Putnam
IPC分类号： H03K19/0175
CPC分类号： H01L27/0266 , H03K17/08142
摘要： A structure and apparatus is provided for an electrostatic discharge power clamp, for use with high voltage power supplies. The power clamp includes a network of transistor devices, for example, nFETs arranged in series between a power rail and a ground rail. The first transistor device is biased into a partially on-state, and thus, neither device sees the full voltage potential between the power rail and the ground rail. Accordingly, the power clamp can function in voltage environments higher than the native voltage of the transistor devices. Additionally, the second transistor device is controlled by an RC network functioning as a trigger which allows the second transistor device to turn on during a voltage spike such as occurs during an ESD event. The capacitor of the RC network may be small thereby requiring small real estate on the integrated circuit. The clamp may have fast turn-on times as well as conducting current for long periods of time after turning on.
摘要翻译：为静电放电电源钳提供一种用于高压电源的结构和装置。功率钳包括晶体管器件网络，例如串联布置在电源轨和接地轨之间的nFET。第一晶体管器件被偏置成部分导通状态，因此，两个器件都不会看到电源轨和接地轨之间的全电压电位。因此，功率钳可以在高于晶体管器件的天然电压的电压环境中工作。此外，第二晶体管器件由用作触发器的RC网络来控制，该RC网络允许第二晶体管器件在诸如在ESD事件期间发生的电压尖峰期间导通。 RC网络的电容器可能很小，从而在集成电路上需要小的空间。打开后，夹具可能会导通快速导通时间，并长时间传导电流。

9. 发明申请

US20050085028A1 Method and structure to suppress external latch-up 审中-公开
标题翻译：抑制外部闩锁的方法和结构
公开(公告)号：US20050085028A1
公开(公告)日：2005-04-21
申请号：US10605699
申请日：2003-10-21
申请人： Kiran Chatty , Peter Cottrell , Robert Gauthier , Mujahid Muhammad
发明人： Kiran Chatty , Peter Cottrell , Robert Gauthier , Mujahid Muhammad
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0921
摘要： A method and structure for protection against latch-up is provided. Integrated circuits manufactured in accordance with the present disclosure feature well and substrate contacts of varying periodicity. Such a strategy enables maximizing the design of an integrated circuit as to the suppression of latch-up while concurrently optimizing available area on the chip allocable to circuit design. This method and structure is particularly beneficial to protect against cable discharge events and other discharge occurrences prone to injecting large current densities into an integrated circuit.
摘要翻译：提供了一种用于防止闩锁的方法和结构。根据本公开制造的集成电路特征良好，并且具有不同周期性的衬底触点。这样的策略能够最大化集成电路的设计，以抑制闩锁，同时优化可分配给电路设计的芯片上的可用区域。该方法和结构特别有利于防止电缆放电事件和易于将大电流密度注入集成电路的其它放电事件。

10. 发明申请

US20050227418A1 METHOD FOR CREATING A SELF-ALIGNED SOI DIODE BY REMOVING A POLYSILICON GATE DURING PROCESSING 失效
标题翻译：通过在加工过程中移除多晶硅栅极创建自对准SOI二极管的方法
公开(公告)号：US20050227418A1
公开(公告)日：2005-10-13
申请号：US10708912
申请日：2004-03-31
申请人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
发明人： Kiran Chatty , Robert Gauthier , Mujahid Muhammad , Christopher Putnam
IPC分类号： H01L21/329 , H01L21/84 , H01L27/02 , H01L27/12 , H01L29/861
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203 , H01L29/66136 , H01L29/861
摘要： A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.
摘要翻译：一种形成自对准SOI二极管的方法，所述方法包括在衬底上沉积保护结构; 在衬底中的至少一对隔离区域之间的区域中注入多个可变掺杂剂类型的扩散区域，所述多个扩散区域被二极管结点隔开，其中所述注入将所述二极管结的上表面与所述保护层结构体; 并移除保护结构。该方法还包括在扩散区上形成硅化物层并与保护结构对准。保护结构包括硬掩模，其中硬掩模包括氮化硅层。或者，保护结构包括在栅极的相对侧上的多晶硅栅极和绝缘间隔物。此外，在去除步骤中，衬垫保留在衬底上。

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