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1. 发明申请

US20100118690A1 Systems and Methods for Sector Address Mark Detection 有权
标题翻译：用于扇区地址标记检测的系统和方法
公开(公告)号：US20100118690A1
公开(公告)日：2010-05-13
申请号：US12270786
申请日：2008-11-13
申请人： Viswanath Annampedu , Venkatram Muddhasani
发明人： Viswanath Annampedu , Venkatram Muddhasani
IPC分类号： G11B7/24
CPC分类号： G11B5/59655 , G11B5/09 , G11B5/59616
摘要： Various embodiments of the present invention provide systems and methods for sector address mark detection. As an example, data detection systems are disclosed that include a sector address mark detection circuit and a sector address mark quality detection circuit. The sector address mark detection circuit receives a data stream and identifies a sector address mark in the data stream. The sector address mark quality detection circuit receives a first sample and a second sample from the data stream corresponding to the sector address mark, and determines a quality of the sector address mark based at least in part on the first sample and the second sample. In various cases, one or more of the samples of the sector address mark up to all of the samples of the sector address mark may be used.
摘要翻译：本发明的各种实施例提供了用于扇区地址标记检测的系统和方法。作为示例，公开了包括扇区地址标记检测电路和扇区地址标记质量检测电路的数据检测系统。扇区地址标记检测电路接收数据流并识别数据流中的扇区地址标记。扇区地址标记质量检测电路从对应于扇区地址标记的数据流接收第一采样和第二采样，并且至少部分地基于第一采样和第二采样来确定扇区地址标记的质量。在各种情况下，可以使用扇区地址标记到扇区地址标记的所有样本的一个或多个样本。

2. 发明授权

US08243381B2 Systems and methods for sector address mark detection 有权
标题翻译：扇区地址标识检测的系统和方法
公开(公告)号：US08243381B2
公开(公告)日：2012-08-14
申请号：US12270786
申请日：2008-11-13
申请人： Viswanath Annampedu , Venkatram Muddhasani
发明人： Viswanath Annampedu , Venkatram Muddhasani
IPC分类号： G11B5/09
CPC分类号： G11B5/59655 , G11B5/09 , G11B5/59616
摘要： Various embodiments of the present invention provide systems and methods for sector address mark detection. As an example, data detection systems are disclosed that include a sector address mark detection circuit and a sector address mark quality detection circuit. The sector address mark detection circuit receives a data stream and identifies a sector address mark in the data stream. The sector address mark quality detection circuit receives a first sample and a second sample from the data stream corresponding to the sector address mark, and determines a quality of the sector address mark based at least in part on the first sample and the second sample. In various cases, one or more of the samples of the sector address mark up to all of the samples of the sector address mark may be used.
摘要翻译：本发明的各种实施例提供了用于扇区地址标记检测的系统和方法。作为示例，公开了包括扇区地址标记检测电路和扇区地址标记质量检测电路的数据检测系统。扇区地址标记检测电路接收数据流并识别数据流中的扇区地址标记。扇区地址标记质量检测电路从对应于扇区地址标记的数据流接收第一采样和第二采样，并且至少部分地基于第一采样和第二采样来确定扇区地址标记的质量。在各种情况下，可以使用扇区地址标记到扇区地址标记的所有样本的一个或多个样本。

3. 发明申请

US20090267819A1 Systems and Methods for Reducing the Effects of ADC Mismatch 有权
标题翻译：减少ADC失配影响的系统和方法
公开(公告)号：US20090267819A1
公开(公告)日：2009-10-29
申请号：US12111294
申请日：2008-04-29
申请人： Viswanath Annampedu , Venkatram Muddhasani
发明人： Viswanath Annampedu , Venkatram Muddhasani
IPC分类号： H03M1/12
CPC分类号： H03M1/0678 , G11B20/10009 , G11B20/10027 , G11B20/10037 , G11B20/10481 , G11B2220/2516 , H03M1/1205
摘要： Various embodiments of the present invention provide systems and methods for utilizing a plurality of potentially mismatched analog to digital converters. For example, a method for adaptively processing a variety of input signals is disclosed. The method includes providing an adaptive loop circuit, and a first and second circuit pairs. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. An input signal is received and an event status is received. The event status initially indicates that the input signal includes data associated with a first event and subsequently indicates that the input signal includes data associated with a second event. The first circuit pair to drive the adaptive loop circuit when the first event is indicated, and the second circuit pair to drive the adaptive circuit when the second event is indicated.
摘要翻译：本发明的各种实施例提供了用于利用多个潜在失配的模数转换器的系统和方法。例如，公开了一种用于自适应地处理各种输入信号的方法。该方法包括提供自适应环路电路以及第一和第二电路对。第一电路对包括第一模数转换器和第一寄存器，第二电路对包括第二模数转换器和第二寄存器。接收输入信号并接收事件状态。事件状态最初指示输入信号包括与第一事件相关联的数据，并且随后指示输入信号包括与第二事件相关联的数据。当指示第一事件时驱动自适应环路电路的第一电路对，以及当指示第二事件时驱动自适应电路的第二电路对。

4. 发明授权

US07813065B2 Systems and methods for acquiring modified rate burst demodulation in servo systems 有权
标题翻译：用于在伺服系统中获取改进的速率脉冲串解调的系统和方法
公开(公告)号：US07813065B2
公开(公告)日：2010-10-12
申请号：US12111319
申请日：2008-04-29
申请人： Viswanath Annampedu , Venkatram Muddhasani , Xun Zhang
发明人： Viswanath Annampedu , Venkatram Muddhasani , Xun Zhang
IPC分类号： G11B20/08 , G11B5/596
CPC分类号： G11B5/59622
摘要： Various embodiments of the present invention provide systems and methods for performing modified rate burst demodulation. For example, a method for performing modified rate burst demodulation is disclosed. The method includes receiving a data input that includes a synchronization pattern, an information pattern, and a demodulation pattern. A periodic boundary is established along with a phase and frequency of a sampling clock based at least in part on the synchronization pattern. The information pattern is processed using the sampling clock to determine a location fix. The sampling clock is phase shifted by a skew amount and a phase shifted sampling clock is provided. The demodulation pattern is processed using the phase shifted sampling clock.
摘要翻译：本发明的各种实施例提供了用于执行修改的速率突发解调的系统和方法。例如，公开了一种用于执行修正速率脉冲串解调的方法。该方法包括接收包括同步模式，信息模式和解调模式的数据输入。至少部分地基于同步模式，建立周期性边界以及采样时钟的相位和频率。使用采样时钟处理信息模式以确定位置锁定。采样时钟相位偏移量，并提供相移采样时钟。使用相移采样时钟来处理解调模式。

5. 发明授权

US07768437B2 Systems and methods for reducing the effects of ADC mismatch 有权
标题翻译：减少ADC失配影响的系统和方法
公开(公告)号：US07768437B2
公开(公告)日：2010-08-03
申请号：US12111294
申请日：2008-04-29
申请人： Viswanath Annampedu , Venkatram Muddhasani
发明人： Viswanath Annampedu , Venkatram Muddhasani
IPC分类号： H03M1/36
CPC分类号： H03M1/0678 , G11B20/10009 , G11B20/10027 , G11B20/10037 , G11B20/10481 , G11B2220/2516 , H03M1/1205
摘要： Various embodiments of the present invention provide systems and methods for utilizing a plurality of potentially mismatched analog to digital converters. For example, a method for adaptively processing a variety of input signals is disclosed. The method includes providing an adaptive loop circuit, and a first and second circuit pairs. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. An input signal is received and an event status is received. The event status initially indicates that the input signal includes data associated with a first event and subsequently indicates that the input signal includes data associated with a second event. The first circuit pair to drive the adaptive loop circuit when the first event is indicated, and the second circuit pair to drive the adaptive circuit when the second event is indicated.
摘要翻译：本发明的各种实施例提供了用于利用多个潜在失配的模数转换器的系统和方法。例如，公开了一种用于自适应地处理各种输入信号的方法。该方法包括提供自适应环路电路以及第一和第二电路对。第一电路对包括第一模数转换器和第一寄存器，第二电路对包括第二模数转换器和第二寄存器。接收输入信号并接收事件状态。事件状态最初指示输入信号包括与第一事件相关联的数据，并且随后指示输入信号包括与第二事件相关联的数据。当指示第一事件时驱动自适应环路电路的第一电路对，以及当指示第二事件时驱动自适应电路的第二电路对。

6. 发明申请

US20090268322A1 Systems and Methods for Acquiring Modified Rate Burst Demodulation in Servo Systems 有权
标题翻译：用于获取伺服系统中改进率爆破解调的系统和方法
公开(公告)号：US20090268322A1
公开(公告)日：2009-10-29
申请号：US12111319
申请日：2008-04-29
申请人： Viswanath Annampedu , Venkatram Muddhasani , Xun Zhang
发明人： Viswanath Annampedu , Venkatram Muddhasani , Xun Zhang
IPC分类号： G11B5/02
CPC分类号： G11B5/59622
摘要： Various embodiments of the present invention provide systems and methods for performing modified rate burst demodulation. For example, a method for performing modified rate burst demodulation is disclosed. The method includes receiving a data input that includes a synchronization pattern, an information pattern, and a demodulation pattern. A periodic boundary is established along with a phase and frequency of a sampling clock based at least in part on the synchronization pattern. The information pattern is processed using the sampling clock to determine a location fix. The sampling clock is phase shifted by a skew amount and a phase shifted sampling clock is provided. The demodulation pattern is processed using the phase shifted sampling clock.
摘要翻译：本发明的各种实施例提供了用于执行修改的速率突发解调的系统和方法。例如，公开了一种用于执行修正速率脉冲串解调的方法。该方法包括接收包括同步模式，信息模式和解调模式的数据输入。至少部分地基于同步模式，建立周期性边界以及采样时钟的相位和频率。使用采样时钟处理信息模式以确定位置锁定。采样时钟相位偏移量，并提供相移采样时钟。使用相移采样时钟来处理解调模式。

7. 发明授权

US09093096B2 Flaw scan circuit for repeatable run out (RRO) data 有权
标题翻译：缺陷扫描电路可重复耗尽（RRO）数据
公开(公告)号：US09093096B2
公开(公告)日：2015-07-28
申请号：US13559744
申请日：2012-07-27
申请人： Viswanath Annampedu
发明人： Viswanath Annampedu
IPC分类号： G06F11/07 , G11B5/596
CPC分类号： G11B5/59627
摘要： Improved flaw scan circuits are provided for repeatable run out data. RRO (repeatable run out) data is processed by counting a number of RRO data bits detected in a servo sector; and setting an RRO flaw flag if at least a specified number of RRO data bits is not detected in the server sector. The RRO flaw flag can also optionally be set by detecting an RRO address mark in the servo sector; counting a number of samples in the servo sector after the RRO address mark that do not satisfy a quality threshold; and setting the RRO flaw flag when the counted number of samples that do not satisfy the quality threshold exceeds a specified flaw threshold. If the RRO flaw flag is set, the RRO data can be discarded, and/or an error recovery mechanism can be implemented to obtain the RRO data.
摘要翻译：提供改进的缺陷扫描电路用于可重复的耗尽数据。通过对在伺服扇区中检测到的RRO数据位的数量进行计数来处理RRO（可重复耗尽）数据; 并且如果在服务器扇区中未检测到至少指定数量的RRO数据位，则设置RRO缺陷标志。还可以通过检测伺服扇区中的RRO地址标记来可选地设置RRO缺陷标志; 在不满足质量阈值的RRO地址标记之后对伺服扇区中的多个样本进行计数; 并且当不满足质量阈值的计数的样本数超过规定的缺陷阈值时，设置RRO缺陷标志。如果设置了RRO缺陷标志，则可以丢弃RRO数据，并且/或者可以实现错误恢复机制以获得RRO数据。

8. 发明申请

US20140029129A1 METHODS AND APPARATUS FOR IMPROVED DETECTION OF SERVO SECTOR DATA USING SINGLE BIT ERROR CORRECTION 有权
标题翻译：使用单位错误校正改进检测伺服系统数据的方法和装置
公开(公告)号：US20140029129A1
公开(公告)日：2014-01-30
申请号：US13559747
申请日：2012-07-27
申请人： Viswanath Annampedu
发明人： Viswanath Annampedu
IPC分类号： G11B20/18 , G11B5/09
CPC分类号： G11B5/59688 , G11B5/59627 , G11B20/18
摘要： Methods and apparatus are provided for improved detection of servo sector data in a magnetic recording system using single bit error correction. Servo sector data is processed by detecting the servo sector data; determining whether a single bit error occurred in the detected servo sector data; and flipping a bit value of an individual bit in the detected servo sector data having a lowest amplitude sample among the samples of the detected servo sector data when a single bit error is detected in the detected servo sector data. The servo sector data comprises, for example, a servo address mark, Gray data, an RRO address mark and/or RRO data. For example, the bit value can be flipped by changing a binary value of one to a binary value of zero and changing a binary value of zero to a binary value of one.
摘要翻译：提供了使用单位错误校正在磁记录系统中改善伺服扇区数据检测的方法和装置。通过检测伺服扇区数据来处理伺服扇区数据; 确定在检测到的伺服扇区数据中是否发生单个位错误; 以及在检测到的伺服扇区数据中检测到单个位错误时，在检测到的伺服扇区数据的样本中，翻转检测到的具有最低振幅采样的伺服扇区数据中的各个位的位值。伺服扇区数据例如包括伺服地址标记，灰色数据，RRO地址标记和/或RRO数据。例如，可以通过将二进制值1改变为二进制值零并将二进制值改变为二进制值1来翻转位值。

9. 发明申请

US20120197920A1 SYSTEMS AND METHODS FOR DIVERSITY COMBINED DATA DETECTION 有权
标题翻译：用于多样性组合数据检测的系统和方法
公开(公告)号：US20120197920A1
公开(公告)日：2012-08-02
申请号：US13014754
申请日：2011-01-27
申请人： Viswanath Annampedu
发明人： Viswanath Annampedu
IPC分类号： G06F17/30
CPC分类号： G11B20/1403 , G11B20/10296 , G11B2020/1281
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits including a pattern detection circuit having at least two data detector circuits each operable to receive the same series of data samples and to provide a first detected data output and a second detected data output, respectively. In addition, the data pattern detection circuit includes a result combining circuit that is operable to assert a pattern found output based at least in part on the first detected data output and the second detected data output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，本发明的一些实施例提供数据处理电路，其包括具有至少两个数据检测器电路的模式检测电路，每个数据检测器电路可操作以接收同一系列数据样本，并提供第一检测数据输出和第二检测数据输出，分别。此外，数据图案检测电路包括结果组合电路，其可操作以至少部分地基于第一检测数据输出和第二检测数据输出来断言发现的输出。

10. 发明申请

US20120155587A1 Systems and Methods for Improved Timing Recovery 有权
标题翻译：改进定时恢复的系统和方法
公开(公告)号：US20120155587A1
公开(公告)日：2012-06-21
申请号：US12972904
申请日：2010-12-20
申请人： Viswanath Annampedu
发明人： Viswanath Annampedu
IPC分类号： H04L7/00 , H03M1/12
CPC分类号： G11B20/10222 , G11B20/10046 , G11B2220/2516 , H04L7/0025 , H04L7/0029 , H04L7/0337
摘要： Various embodiments of the present invention provide systems and methods for timing recovery. As an example, timing recovery circuits include: a first digital interpolation circuit, a second digital interpolation circuit, a phase selection circuit, and a sampling clock rotation circuit. The first digital interpolation circuit is operable to receive a data input and to provide a first interpolated output corresponding to a first phase, and the second digital interpolation circuit is operable to receive the data input and to provide a second interpolated output corresponding to a second phase. The phase selection circuit operable to select the first phase for processing, and the sampling clock rotation circuit is operable to move a sampling clock away from the first phase.
摘要翻译：本发明的各种实施例提供了用于定时恢复的系统和方法。作为示例，定时恢复电路包括：第一数字内插电路，第二数字内插电路，相位选择电路和采样时钟旋转电路。第一数字内插电路可操作以接收数据输入并提供对应于第一相位的第一内插输出，并且第二数字内插电路可操作以接收数据输入并提供对应于第二相位的第二内插输出。所述相位选择电路可操作以选择所述第一相进行处理，并且所述采样时钟旋转电路可操作以将取样时钟移动离开所述第一相位。

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