专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06764967B2 Method for forming low thermal budget sacrificial oxides 失效
标题翻译：形成低热预算牺牲氧化物的方法
公开(公告)号：US06764967B2
公开(公告)日：2004-07-20
申请号：US10264489
申请日：2002-10-05
申请人： Vincent Pai , Kuo-Chi Tu , Chung-Wei Chang , Chia-Shiung Tsai , Chun-Yao Chen
发明人： Vincent Pai , Kuo-Chi Tu , Chung-Wei Chang , Chia-Shiung Tsai , Chun-Yao Chen
IPC分类号： H01L2131
CPC分类号： H01L21/28238 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31675 , Y10S438/906
摘要： A method for forming a silicon dioxide layer over a silicon substrate including providing a substrate having exposed silicon portions; and, forming a silicon dioxide layer over the exposed silicon portions according to an oxide formation process including contacting the exposed silicon portions with an oxidizing solution comprising water and ozone.
摘要翻译：一种在硅衬底上形成二氧化硅层的方法，包括提供具有暴露的硅部分的衬底; 以及根据氧化物形成过程在暴露的硅部分上形成二氧化硅层，包括使暴露的硅部分与包含水和臭氧的氧化溶液接触。

2. 发明授权

US06833578B1 Method and structure improving isolation between memory cell passing gate and capacitor 有权
标题翻译：存储单元通过栅极和电容器之间的隔离方法和结构
公开(公告)号：US06833578B1
公开(公告)日：2004-12-21
申请号：US10733216
申请日：2003-12-11
申请人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu , Chung-Wei Chang , Tien-Lu Lin , Kuo-Ching Huang , Wen-Cheng Chen , Tsung-Hsun Huang , Hsiao-Hui Tseng
发明人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu , Chung-Wei Chang , Tien-Lu Lin , Kuo-Ching Huang , Wen-Cheng Chen , Tsung-Hsun Huang , Hsiao-Hui Tseng
IPC分类号： H01L27108
CPC分类号： H01L28/57 , H01L27/11 , H01L28/90
摘要： A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.
摘要翻译：一种存储单元，包括具有插入第一和第二垂直设置的电极的介电层的电容器，位于电容器上方的绝缘衬垫，以及通过电容器的晶体管栅极延伸。间隔件将电容器电极之一的端部与晶体管栅极延伸部隔离。在一个实施例中，间隔件包括构造成接合包括电容器电极之一和绝缘衬里的端部的第二非平面轮廓的第一非平面轮廓。

3. 发明申请

US20070200162A1 Reducing dielectric constant for MIM capacitor 有权
标题翻译：降低MIM电容的介电常数
公开(公告)号：US20070200162A1
公开(公告)日：2007-08-30
申请号：US11361330
申请日：2006-02-24
申请人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
发明人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
IPC分类号： H01L29/76
CPC分类号： H01L28/40 , H01L27/10852 , H01L27/10894 , H01L28/56
摘要： A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.
摘要翻译：提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于最少部分地被第三介电层填充。存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。位线电耦合到电容器。优选地，在电容器的杯区域中形成具有大尺寸的空隙。

4. 发明授权

US08242551B2 Metal-insulator-metal structure for system-on-chip technology 有权
标题翻译：金属 - 绝缘体 - 金属结构的片上系统技术
公开(公告)号：US08242551B2
公开(公告)日：2012-08-14
申请号：US12397948
申请日：2009-03-04
申请人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
发明人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
IPC分类号： H01G4/40 , H01G17/00
CPC分类号： H01L27/0805 , H01L27/0629 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

5. 发明授权

US07382012B2 Reducing parasitic capacitance of MIM capacitor in integrated circuits by reducing effective dielectric constant of dielectric layer 有权
标题翻译：通过降低介电层的有效介电常数，降低集成电路中MIM电容的寄生电容
公开(公告)号：US07382012B2
公开(公告)日：2008-06-03
申请号：US11361330
申请日：2006-02-24
申请人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
发明人： Kuo-Chi Tu , Chun-Yao Chen , Yi-Ching Lin
IPC分类号： H01L27/108 , H01L21/20 , G11C11/00
CPC分类号： H01L28/40 , H01L27/10852 , H01L27/10894 , H01L28/56
摘要： A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.
摘要翻译：提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于最少部分地被第三介电层填充。存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。位线电耦合到电容器。优选地，在电容器的杯区域中形成具有大尺寸的空隙。

6. 发明申请

US20080122032A1 Semiconductor devices with MIM-type decoupling capacitors and fabrication method thereof 审中-公开
标题翻译：具有MIM型去耦电容器的半导体器件及其制造方法
公开(公告)号：US20080122032A1
公开(公告)日：2008-05-29
申请号：US11504693
申请日：2006-08-16
申请人： Kuo-Chi Tu , Chun-Yao Chen
发明人： Kuo-Chi Tu , Chun-Yao Chen
IPC分类号： H01L29/00 , H01L21/02
CPC分类号： H01L28/91 , H01L28/55
摘要： A semiconductor device. The semiconductor device includes a substrate having an array region and a decoupling region, a first dielectric layer overlying the substrate, a second dielectric layer overlying the first dielectric layer, a plurality of active components formed in the first dielectric layer within the array region, a first capacitor formed in the second dielectric layer within the array region, a second capacitor formed in the second dielectric layer within the decoupling region, and a first plug formed in the first dielectric layer within the array region electrically connecting the active component and the first capacitor. The invention also provides a method of fabricating the semiconductor device.
摘要翻译：半导体器件。半导体器件包括具有阵列区和去耦区的衬底，覆盖衬底的第一电介质层，覆盖第一电介质层的第二电介质层，形成在阵列区域内的第一电介质层中的多个有源元件，形成在阵列区域内的第二电介质层中的第一电容器，形成在去耦区域内的第二电介质层中的第二电容器和形成在阵列区域内的第一电介质层中的电连接有源部件和第一电容器。本发明还提供一种制造半导体器件的方法。

7. 发明授权

US06720232B1 Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure 有权
标题翻译：制造金属 - 绝缘体 - 金属（MIM）电容器结构的嵌入式DRAM的方法
公开(公告)号：US06720232B1
公开(公告)日：2004-04-13
申请号：US10411347
申请日：2003-04-10
申请人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu
发明人： Kuo-Chi Tu , Chun-Yao Chen , Huey-Chi Chu
IPC分类号： H01L2120
CPC分类号： H01L27/10852 , H01L27/10811 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.
摘要翻译：描述了在嵌入式DRAM工艺中制造金属 - 绝缘体 - 金属电容器的方法。多个接触插塞通过绝缘层提供到衬底中的半导体器件结构，其中接触插塞形成在衬底的逻辑区域中并且在衬底的存储区域中并且将节点接触插塞提供到衬底内的节点接触区域底物在记忆区。此后，电容器在自对准铜工艺中以扭曲的沟槽制造。

8. 发明申请

US20100224925A1 METAL-INSULATOR-METAL STRUCTURE FOR SYSTEM-ON-CHIP TECHNOLOGY 有权
标题翻译：金属绝缘子金属结构系统芯片技术
公开(公告)号：US20100224925A1
公开(公告)日：2010-09-09
申请号：US12397948
申请日：2009-03-04
申请人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
发明人： Kuo-Cheng Ching , Kuo-Chi Tu , Chun-Yao Chen
IPC分类号： H01L27/108 , H01L29/92 , H01L21/02
CPC分类号： H01L27/0805 , H01L27/0629 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底中的隔离结构，在隔离结构上形成的导电层，以及形成在隔离结构上的金属 - 绝缘体 - 金属（MIM）电容器。 MIM电容器具有冠状形状，其包括顶部电极，第一底部电极和设置在顶部电极和第一底部电极之间的电介质，第一底部电极至少延伸到导电层的顶表面。

9. 发明授权

US07271083B2 One-transistor random access memory technology compatible with metal gate process 有权
标题翻译：单晶体管随机存取技术兼容金属栅极工艺
公开(公告)号：US07271083B2
公开(公告)日：2007-09-18
申请号：US10896491
申请日：2004-07-22
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Y. Shen , Chun-Yao Chen , Hsiang-Fan Lee
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Chung-Yi Chen , C. Y. Shen , Chun-Yao Chen , Hsiang-Fan Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/10861 , H01L27/10873
摘要： One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.
摘要翻译：与金属栅极工艺兼容的单晶体管RAM技术制造由与MIM电容器嵌入式隔离结构的顶部电极相同的金属材料形成的金属栅电极。栅极电介质层由与MIM电容器嵌入式隔离结构的电容器电介质相同的高k电介质材料形成。

10. 发明申请

US20050082586A1 MIM capacitor structure and method of manufacture 有权
标题翻译： MIM电容器结构及制造方法
公开(公告)号：US20050082586A1
公开(公告)日：2005-04-21
申请号：US10689294
申请日：2003-10-20
申请人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
发明人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/76 , H01L21/20
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion of the top insulating layer is recessed in a region between at least two adjacent MIM capacitor patterns. When the top plate material of the MIM capacitors is deposited, the top plate material fills the recessed area of the top insulating layer between the adjacent MIM capacitor pattern, forming a connecting region that couples together the top plates of the adjacent MIM capacitors. A portion of the MIM capacitor bottom electrode may be formed in a first metallization layer of the semiconductor device.
摘要翻译：金属绝缘体金属（MIM）电容器结构及其制造方法。多个MIM电容器图案形成在两个或更多个绝缘层中。绝缘层可以包括半导体器件的通孔层和金属化层。顶部绝缘层的顶部凹陷在至少两个相邻的MIM电容器图案之间的区域中。当MIM电容器的顶板材料沉积时，顶板材料填充相邻MIM电容器图案之间的顶部绝缘层的凹陷区域，形成将相邻的MIM电容器的顶板耦合在一起的连接区域。 MIM电容器底部电极的一部分可以形成在半导体器件的第一金属化层中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式